RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Reset and clock control for (RCC) Bits 27:15 Reserved, must be kept at reset value. Bits 14:6 PLLI2SN: PLLI2S multiplication factor for VCO Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the PLLI2S is disabled. Only half-word and word accesses are allowed to write these bits. Caution: The software has to set these bits correctly to ensure that the VCO output frequency is between 192 and 432 MHz. VCO output frequency = VCO input frequency × PLLI2SN with 192 ≤ PLLI2SN ≤ 432 000000000: PLLI2SN = 0, wrong configuration 000000001: PLLI2SN = 1, wrong configuration ... 011000000: PLLI2SN = 192 011000001: PLLI2SN = 193 011000010: PLLI2SN = 194 ... 110110000: PLLI2SN = 432 110110000: PLLI2SN = 433, wrong configuration ... 111111111: PLLI2SN = 511, wrong configuration Bits 5:0 Reserved, must be kept at reset value. 6.3.31 RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR) This register is available only on STM32F42x and STM32F43x devices. Address offset: 0x8C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TIMPRE rw Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits 31:25 Reserved, must be kept at reset value. Bit 24 TIMPRE: Timers clocks prescalers selection Set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domain. 0: If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) is configured to a division factor of 1, TIMxCLK = HCKL . Otherwise, the timer clock frequencies are set to twice to the frequency of the APB domain to which the timers are connected: TIMxCLK = 2xPCLKx. 1:If the APB prescaler ( PPRE1, PPRE2 in the RCC_CFGR register) is configured to a division factor of 1 or 2, TIMxCLK = HCKL. Otherwise, the timer clock frequencies are set to four times to the frequency of the APB domain to which the timers are connected: TIMxCLK = 4xPCLKx. Bits 23: 0 Reserved, must be kept at reset value. Doc ID 018909 Rev 3 180/1416
Reset and clock control for (RCC) <strong>RM0090</strong> 6.3.32 RCC register map Table 25 gives the register map and reset values. Table 25. RCC register map and reset values for STM32F40x and STM32F41x Addr. offset Register name 31 0x00 RCC_CR Reserved 0x04 RCC_PLLCF GR 0x08 RCC_CFGR MCO2 1 MCO2 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MCO2PRE2 MCO2PRE1 PLL I2SRDY PLL I2SON PLLQ 3 PLLQ 2 MCO2PRE0 MCO1PRE2 0x0C RCC_CIR Reserved 0x10 0x14 0x18 RCC_AHB1R STR RCC_AHB2R STR RCC_AHB3R STR Reserved OTGHSRST Reserved PLL RDY PLL ON PLLQ 1 PLLQ 0 MCO1PRE1 MCO1PRE0 Reserved PLLSRC I2SSRC MCO1 1 Reserved MCO1 0 RTCPRE 4 CSSON HSEBYP Reserved RTCPRE 3 RTCPRE 2 HSERDY HSEON PLLP 1 PLLP 0 RTCPRE 1 RTCPRE 0 181/1416 Doc ID 018909 Rev 3 ETHMACRST Reserved CSSC Reserved DMA2RST DMA1RST PLLI2SRDYC PLLRDYC HSERDYC HSIRDYC Reserved LSERDYC LSIRDYC Reserved HSICAL 7 HSICAL 6 Reserved PLLN 8 PPRE2 2 PPRE2 1 Reserved 0x1C Reserved Reserved 0x20 0x24 RCC_APB1R STR RCC_APB2R STR Reserved DACRST PWRRST Reserved CAN2RST CAN1RST Reserved I2C3RST I2C2RST Reserved I2C1RST UART5RST UART4RST Reserved UART3RST UART2RST Reserved SPI3RST SPI2RST TIM11RST TIM10RST TIM9RST Reserved 0x28 Reserved Reserved 0x2C Reserved Reserved 0x30 0x34 0x38 RCC_AHB1E NR RCC_AHB2E NR RCC_AHB3E NR Reserved OTGHSULPIEN OTGHSEN ETHMACPTPEN ETHMACRXEN ETHMACTXEN ETHMACEN Reserved DMA2EN DMA1EN CCMDATARAMEN Reserved Reserved BKPSRAMEN Reserved Reserved 0x3C Reserved Reserved SYSCFGRST Reserved HSICAL 5 HSICAL 4 PLLN 7 PLLN 6 PPRE2 0 PPRE1 2 PLLI2SRDYIE PLLRDYIE Reserved CRCRST HSICAL 3 HSICAL 2 PLLN 5 PLLN 4 PPRE1 1 PPRE1 0 HSERDYIE HSIRDYIE WWDGRST SPI1RST SDIORST CRCEN Reserved Reserved Reserved Reserved HSICAL 1 HSICAL 0 PLLN 3 PLLN 2 Reserved LSERDYIE LSIRDYIE HSITRIM 4 HSITRIM 3 PLLN 1 PLLN 0 HPRE 3 HPRE 2 CSSF GPIOIRST GPIOHRST TIM14RST TIM13RST ADCRST GPIOIEN GPIOHEN Reserved GPIOGRST GPIOFRST HSITRIM 2 HSITRIM 1 PLLM 5 PLLM 4 HSITRIM 0 Reserved HSIRDY HSION PLLM 3 PLLM 2 PLLM 1 PLLM 0 HPRE 1 HPRE 0 SWS 1 SWS 0 SW 1 SW 0 PLLI2SRDYF PLLRDYF OTGFSRST RNGRST HSAHRST CRYPRST Reserved TIM12RST TIM7RST GPIOGEN GPIOFEN USART6RST USART1RST OTGFSEN RNGEN HASHEN CRYPEN GPIOERST GPIODRST TIM6RST TIM5RST GPIOEEN GPIODEN HSERDYF HSIRDYF Reserved GPIOCRST GPIOBRST Reserved TIM4RST TIM3RST GPIOCEN GPIOBEN Reserved LSERDYF LSIRDYF GPIOARST DCMIRST FSMCRST TIM2RST TIM8RST TIM1RST GPIOAEN DCMIEN FSMCEN
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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Reset and clock control for (RCC) R
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DMA controller (DMA) RM0090 9.3.17
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 15 14 1
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DMA controller (DMA) RM0090 9.5.11
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DMA controller (DMA) RM0090 Table 4
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Table 22
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 33.11 Ca
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 33.15.3
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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show all

RM0090: Reference manual - STMicroelectronics

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