RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Interrupts and events Table 44. Vector table for STM32F42x and STM32F43x Position Priority Type of priority 54 61 settable TIM6_DAC TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts 0x0000 0118 55 62 settable TIM7 TIM7 global interrupt 0x0000 011C 56 63 settable DMA2_Stream0 DMA2 Stream0 global interrupt 0x0000 0120 57 64 settable DMA2_Stream1 DMA2 Stream1 global interrupt 0x0000 0124 58 65 settable DMA2_Stream2 DMA2 Stream2 global interrupt 0x0000 0128 59 66 settable DMA2_Stream3 DMA2 Stream3 global interrupt 0x0000 012C 60 67 settable DMA2_Stream4 DMA2 Stream4 global interrupt 0x0000 0130 61 68 settable ETH Ethernet global interrupt 0x0000 0134 62 69 settable ETH_WKUP Ethernet Wakeup through EXTI line interrupt 0x0000 0138 63 70 settable CAN2_TX CAN2 TX interrupts 0x0000 013C 64 71 settable CAN2_RX0 CAN2 RX0 interrupts 0x0000 0140 65 72 settable CAN2_RX1 CAN2 RX1 interrupt 0x0000 0144 66 73 settable CAN2_SCE CAN2 SCE interrupt 0x0000 0148 67 74 settable OTG_FS USB On The Go FS global interrupt 0x0000 014C 68 75 settable DMA2_Stream5 DMA2 Stream5 global interrupt 0x0000 0150 69 76 settable DMA2_Stream6 DMA2 Stream6 global interrupt 0x0000 0154 70 77 settable DMA2_Stream7 DMA2 Stream7 global interrupt 0x0000 0158 71 78 settable USART6 USART6 global interrupt 0x0000 015C 72 79 settable I2C3_EV I 2 C3 event interrupt 0x0000 0160 73 80 settable I2C3_ER I 2 C3 error interrupt 0x0000 0164 74 81 settable OTG_HS_EP1_ OUT 75 82 settable OTG_HS_EP1_I N 76 83 settable OTG_HS_WKUP 77 84 settable OTG_HS Acronym Description Address USB On The Go HS End Point 1 Out global interrupt USB On The Go HS End Point 1 In global interrupt USB On The Go HS Wakeup through EXTI interrupt USB On The Go HS global interrupt 0x0000 0168 0x0000 016C 0x0000 0170 0x0000 0174 78 85 settable DCMI DCMI global interrupt 0x0000 0178 79 86 settable CRYP CRYP crypto global interrupt 0x0000 017C 80 87 settable HASH_RNG Hash and Rng global interrupt 0x0000 0180 81 88 Settable FPU FPU global interrupt 0x0000 0184 Doc ID 018909 Rev 3 254/1416
Interrupts and events <strong>RM0090</strong> Table 44. Vector table for STM32F42x and STM32F43x Position Priority Type of priority 82 89 settable UART7 UART 7 global interrupt 0x0000 0188 83 90 settable UART8 UART 8 global interrupt 0x0000 018C 84 91 settable SPI4 SPI 4 global interrupt 0x0000 0190 85 92 settable SPI5 SPI 5 global interrupt 0x0000 0194 86 93 settable SPI6 SPI 6 global interrupt 0x0000 0198 10.2.1 EXTI main features The main features of the EXTI controller are the following: ● independent trigger and mask on each interrupt/event line ● dedicated status bit for each interrupt line ● generation of up to 23 software event/interrupt requests ● detection of external signals with a pulse width lower than the APB2 clock period. Refer to the electrical characteristics section of the STM32F4xx datasheets for details on this parameter. 255/1416 Doc ID 018909 Rev 3 Acronym Description Address
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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Reset and clock control for (RCC) R
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General-purpose I/Os (GPIO) RM0090
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Analog-to-digital converter (ADC) R
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Digital-to-analog converter (DAC) R
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Digital camera interface (DCMI) RM0
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Cryptographic processor (CRYP) RM00
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 The as
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Real-time clock (RTC) RM0090 23.3.5
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Real-time clock (RTC) RM0090 Bit 3
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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