RM0090: Reference manual - STMicroelectronics

Ethernet (ETH): media access control (MAC) with DMA controller RM0090
addressed buffers, instead of two contiguous buffers in memory. A data buffer resides in the
Host’s physical memory space, and consists of an entire frame or part of a frame, but cannot
exceed a single frame. Buffers contain only data. The buffer status is maintained in the
descriptor. Data chaining refers to frames that span multiple data buffers. However, a single
descriptor cannot span multiple frames. The DMA skips to the next frame buffer when the
end of frame is detected. Data chaining can be enabled or disabled. The descriptor ring and
chain structure is shown in Figure 346.
Figure 346. Descriptor ring and chain structure
Descriptor 0
Descriptor 1
Descriptor 2
Descriptor n
29.6.1 Initialization of a transfer using DMA
Initialization for the MAC is as follows:
1. Write to ETH_DMABMR to set STM32F4xx bus access parameters.
2. Write to the ETH_DMAIER register to mask unnecessary interrupt causes.
3. The software driver creates the transmit and receive descriptor lists. Then it writes to
both the ETH_DMARDLAR and ETH_DMATDLAR registers, providing the DMA with
the start address of each list.
4. Write to MAC Registers 1, 2, and 3 to choose the desired filtering options.
5. Write to the MAC ETH_MACCR register to configure and enable the transmit and
receive operating modes. The PS and DM bits are set based on the auto-negotiation
result (read from the PHY).
6. Write to the ETH_DMAOMR register to set bits 13 and 1 and start transmission and
reception.
7. The transmit and receive engines enter the running state and attempt to acquire
descriptors from the respective descriptor lists. The receive and transmit engines then
begin processing receive and transmit operations. The transmit and receive processes
are independent of each other and can be started or stopped separately.
29.6.2 Host bus burst access
The DMA attempts to execute fixed-length burst transfers on the AHB master interface if
configured to do so (FB bit in ETH_DMABMR). The maximum burst length is indicated and
limited by the PBL field (ETH_DMABMR [13:8]). The receive and transmit descriptors are
941/1416 Doc ID 018909 Rev 3
Ring structure Chain structure
Buffer 1
Buffer 2
Buffer 1
Buffer 2
Buffer 1
Buffer 2
Buffer 1
Buffer 2
Descriptor 0
Descriptor 1
Descriptor 2
Next descriptor
Buffer 1
Buffer 1
Buffer 1
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