RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Controller area network (bxCAN) 24.8 bxCAN interrupts Four interrupt vectors are dedicated to bxCAN. Each interrupt source can be independently enabled or disabled by means of the CAN Interrupt Enable Register (CAN_IER). Figure 237. Event flags and interrupt generation RQCP0 CAN_TSR RQCP1 + RQCP2 CAN_RF0R CAN_RF1R CAN_ESR CAN_MSR FMP0 FULL0 FOVR0 FMP1 FULL1 FOVR1 EWGF EPVF BOFF 1≤LEC≤6 WKUI SLAKI CAN_IER TMEIE FMPIE0 FFIE0 FOVIE0 FMPIE1 FFIE1 FOVIE1 ERRIE EWGIE EPVIE BOFIE LECIE WKUIE SLKIE & & & & & & & & & & & TRANSMIT INTERRUPT ● The transmit interrupt can be generated by the following events: – Transmit mailbox 0 becomes empty, RQCP0 bit in the CAN_TSR register set. – Transmit mailbox 1 becomes empty, RQCP1 bit in the CAN_TSR register set. – Transmit mailbox 2 becomes empty, RQCP2 bit in the CAN_TSR register set. ● The FIFO 0 interrupt can be generated by the following events: – Reception of a new message, FMP0 bits in the CAN_RF0R register are not ‘00’. – FIFO0 full condition, FULL0 bit in the CAN_RF0R register set. – FIFO0 overrun condition, FOVR0 bit in the CAN_RF0R register set. ● The FIFO 1 interrupt can be generated by the following events: – Reception of a new message, FMP1 bits in the CAN_RF1R register are not ‘00’. – FIFO1 full condition, FULL1 bit in the CAN_RF1R register set. + + + FIFO 0 INTERRUPT FIFO 1 INTERRUPT ERRI CAN_MSR Doc ID 018909 Rev 3 678/1416 & & & + STATUS CHANGE ERROR INTERRUPT
Controller area network (bxCAN) <strong>RM0090</strong> – FIFO1 overrun condition, FOVR1 bit in the CAN_RF1R register set. ● The error and status change interrupt can be generated by the following events: 24.9 CAN registers – Error condition, for more details on error conditions please refer to the CAN Error Status register (CAN_ESR). – Wakeup condition, SOF monitored on the CAN Rx signal. – Entry into Sleep mode. The peripheral registers have to be accessed by words (32 bits). 24.9.1 Register access protection Erroneous access to certain configuration registers can cause the hardware to temporarily disturb the whole CAN network. Therefore the CAN_BTR register can be modified by software only while the CAN hardware is in initialization mode. Although the transmission of incorrect data will not cause problems at the CAN network level, it can severely disturb the application. A transmit mailbox can be only modified by software while it is in empty state, refer to Figure 229: Transmit mailbox states. The filter values can be modified either deactivating the associated filter banks or by setting the FINIT bit. Moreover, the modification of the filter configuration (scale, mode and FIFO assignment) in CAN_FMxR, CAN_FSxR and CAN_FFAR registers can only be done when the filter initialization mode is set (FINIT=1) in the CAN_FMR register. 24.9.2 CAN control and status registers Refer to Section 1.1 for a list of abbreviations used in register descriptions. CAN master control register (CAN_MCR) Address offset: 0x00 Reset value: 0x0001 0002 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET TTCM ABOM AWUM NART RFLM TXFP SLEEP INRQ Reserved rs rw rw rw rw rw rw rw rw Bits 31:17 Reserved, must be kept at reset value. Bit 16 DBF: Debug freeze 0: CAN working during debug 1: CAN reception/transmission frozen during debug. Reception FIFOs can still be accessed/controlled normally. 679/1416 Doc ID 018909 Rev 3 DBF rw
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Real-time clock (RTC) RM0090 23.2 R
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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