RM0090: Reference manual - STMicroelectronics

RM0090 Flexible static memory controller (FSMC)
Table 218. 16-bit PC-Card signals and access type (continued)
nCE2
nCE1
nREG
nOE/nWE
nIORD /nIOWR
A10
1 0 0 1 0 X X X-X 0
1 0 0 1 0 X X X-X 1 Write Odd Byte on D7-0 YES
I/O space
0 0 0 1 0 X X X-X 0 Read Word on D15-0 YES
The FSMC Bank 4 gives access to those 3 memory spaces as described in Section 32.4.2:
NAND/PC Card address mapping - Table 185: Memory mapping and timing registers
Wait Feature
A9
A7-1
A0
Space Access Type
Read Even Byte on D7-0 YES
1 0 0 1 0 X X X-X 1 Read Odd Byte on D7-0 YES
1 0 0 1 0 X X X-X 0 Write Even Byte on D7-0 YES
0 0 0 1 0 X X X-X 0 Write word on D15-0 YES
0 1 0 1 0 X X X-X X Read Odd Byte on D15-8 Not supported
0 1 0 1 0 X X X-X X Write Odd Byte on D15-8 Not supported
The CompactFlash Storage or PC Card may request the FSMC to extend the length of the
access phase programmed by MEMWAITx/ATTWAITx/IOWAITx bits, asserting the nWAIT
signal after nOE/nWE or nIORD/nIOWR activation if the wait feature is enabled through the
PWAITEN bit in the FSMC_PCRx register. In order to detect the nWAIT assertion correctly,
the MEMWAITx/ATTWAITx/IOWAITx bits must be programmed as follows:
xxWAITx >= 4 + max_wait_assertion_time/HCLK
Allowed/not
Allowed
Where max_wait_assertion_time is the maximum time taken by NWAIT to go low once
nOE/nWE or nIORD/nIOWR is low.
After the de-assertion of nWAIT, the FSMC extends the WAIT phase for 4 HCLK clock
cycles.
Doc ID 018909 Rev 3 1358/1416