RM0090: Reference manual - STMicroelectronics

Advanced-control timers (TIM1&TIM8) RM0090
Figure 99. Output stage of capture/compare channel (channel 1 to 3)
ETR
CNT>CCR1
Output mode OC1REF
CNT=CCR1 controller
OC1CE OC1M[2:0]
TIM1_CCMR1
Figure 100. Output stage of capture/compare channel (channel 4)
ETR
CNT > CCR4
Output mode
CNT = CCR4 controller
OC2M[2:0]
TIM1_CCMR2
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
14.3.6 Input capture mode
OC4 REF
To the master mode
controller
‘0’
Dead-time
generator
DTG[7:0]
TIM1_BDTR
OC1_DT
OC1N_DT
To the master mode
controller
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’.
367/1416 Doc ID 018909 Rev 3
‘0’
x0
01
11
11
10
0x
CC1NECC1E
TIM1_CCER
0
1
CC1P
TIM1_CCER
0
1
Output
enable
circuit
Output
enable
circuit
OC1
OC1N
CC1NE CC1E TIM1_CCER
CC1NP MOEOSSI OSSRTIM1_BDTR
TIM1_CCER
0
1
CC4P
TIM1_CCER
Output
enable
circuit
OC4
CC4E TIM1_CCER
MOEOSSI
TIM1_BDTR
OIS4
TIM1_CR2