RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Embedded Flash memory interface Table 16. Flash register map and reset values (STM32F42x and STM32F43x) (continued) Offset Register 31 0x14 0x18 FLASH_OPTCR Reserved nWRP[11:0] RDP[7:0] Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 1 FLASH_OPTCR 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved nWRP[11:0] Reset value 1 1 1 1 1 1 1 1 1 1 1 1 nRST_STDBY nRST_STOP Reserved WDG_SW Reserved Doc ID 018909 Rev 3 86/1416 BOR_LEV OPTSTRT OPTLOCK
CRC calculation unit <strong>RM0090</strong> 4 CRC calculation unit This section applies to the whole STM32F4xx family, unless otherwise specified. 4.1 CRC introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 4.2 CRC main features ● Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7 – X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2 + X +1 ● Single input/output 32-bit data register ● CRC computation done in 4 AHB clock cycles (HCLK) ● General-purpose 8-bit register (can be used for temporary storage) The block diagram is shown in Figure 6. Figure 6. CRC calculation unit block diagram 32-bit (write access) 4.3 CRC functional description AHB bus Data register (output) The CRC calculation unit mainly consists of a single 32-bit data register, which: ● is used as an input register to enter new data in the CRC calculator (when writing into the register) ● holds the result of the previous CRC calculation (when reading the register) 87/1416 Doc ID 018909 Rev 3 32-bit (read access) CRC computation (polynomial: 0x4C11DB7) Data register (input) ai14968
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 12.4.2 Independent
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Debug support (DBG) RM0090 33 Debug
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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