RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> USB on-the-go high-speed (OTG_HS) Table 176. Core global control and status registers (CSRs) (continued) Acronym OTG_HS_GINTSTS 0x014 OTG_HS core interrupt register (OTG_HS_GINTSTS) on page 1190 OTG_HS_GINTMSK 0x018 OTG_HS interrupt mask register (OTG_HS_GINTMSK) on page 1194 OTG_HS_GRXSTSR 0x01C OTG_HS_GRXSTSP 0x020 Host-mode CSR map OTG_HS Receive status debug read/OTG status read and pop registers (OTG_HS_GRXSTSR/OTG_HS_GRXSTSP) on page 1197 OTG_HS_GRXFSIZ 0x024 OTG_HS Receive FIFO size register (OTG_HS_GRXFSIZ) on page 1198 OTG_HS_GNPTXFSIZ/ OTG_HS_TX0FSIZ 0x028 OTG_HS_GNPTXSTS 0x02C OTG_HS_GCCFG 0x038 OTG_HS nonperiodic transmit FIFO size/Endpoint 0 transmit FIFO size register (OTG_HS_GNPTXFSIZ/OTG_HS_TX0FSIZ) on page 1199 OTG_HS nonperiodic transmit FIFO/queue status register (OTG_HS_GNPTXSTS) on page 1199 OTG_HS general core configuration register (OTG_HS_GCCFG) on page 1202 OTG_HS_CID 0x03C OTG_HS core ID register (OTG_HS_CID) on page 1203 OTG_HS_HPTXFSIZ 0x100 OTG_HS_DIEPTXFx Address offset 0x104 0x124 ... 0x13C OTG_HS Host periodic transmit FIFO size register (OTG_HS_HPTXFSIZ) on page 1203 OTG_HS device IN endpoint transmit FIFO size register (OTG_HS_DIEPTXFx) (x = 1..7, where x is the FIFO_number) on page 1203 These registers must be programmed every time the core changes to host mode. Table 177. Host-mode control and status registers (CSRs) Acronym Offset address Register name Register name OTG_HS_HCFG 0x400 OTG_HS host configuration register (OTG_HS_HCFG) on page 1204 OTG_HS_HFIR 0x404 OTG_HS Host frame interval register (OTG_HS_HFIR) on page 1205 OTG_HS_HFNUM 0x408 OTG_HS_HPTXSTS 0x410 OTG_HS_HAINT 0x414 OTG_HS_HAINTMSK 0x418 OTG_HS host frame number/frame time remaining register (OTG_HS_HFNUM) on page 1205 OTG_HS_Host periodic transmit FIFO/queue status register (OTG_HS_HPTXSTS) on page 1206 OTG_HS Host all channels interrupt register (OTG_HS_HAINT) on page 1207 OTG_HS host all channels interrupt mask register (OTG_HS_HAINTMSK) on page 1207 Doc ID 018909 Rev 3 1176/1416
USB on-the-go high-speed (OTG_HS) <strong>RM0090</strong> Table 177. Host-mode control and status registers (CSRs) (continued) Acronym OTG_HS_HPRT 0x440 OTG_HS_HCCHARx 0x500 0x520 ... 0x6E0 OTG_HS_HCSPLTx 0x504 OTG_HS_HCINTx 0x508 OTG_HS_HCINTMSKx 0x50C OTG_HS_HCTSIZx 0x510 OTG_HS_HCDMAx 0x514 Offset address Device-mode CSR map These registers must be programmed every time the core changes to peripheral mode. Table 178. Device-mode control and status registers Acronym OTG_HS_DCFG 0x800 1177/1416 Doc ID 018909 Rev 3 Register name OTG_HS host port control and status register (OTG_HS_HPRT) on page 1208 OTG_HS host channel-x characteristics register (OTG_HS_HCCHARx) (x = 0..11, where x = Channel_number) on page 1210 OTG_HS host channel-x split control register (OTG_HS_HCSPLTx) (x = 0..11, where x = Channel_number) on page 1212 OTG_HS host channel-x interrupt register (OTG_HS_HCINTx) (x = 0..11, where x = Channel_number) on page 1213 OTG_HS host channel-x interrupt mask register (OTG_HS_HCINTMSKx) (x = 0..11, where x = Channel_number) on page 1214 OTG_HS host channel-x transfer size register (OTG_HS_HCTSIZx) (x = 0..11, where x = Channel_number) on page 1215 OTG_HS host channel-x DMA address register (OTG_HS_HCDMAx) (x = 0..11, where x = Channel_number) on page 1216 Offset address Register name OTG_HS device configuration register (OTG_HS_DCFG) on page 1216 OTG_HS_DCTL 0x804 OTG_HS device control register (OTG_HS_DCTL) on page 1218 OTG_HS_DSTS 0x808 OTG_HS device status register (OTG_HS_DSTS) on page 1220 OTG_HS_DIEPMSK 0x810 OTG_HS_DOEPMSK 0x814 OTG_HS_DAINT 0x818 OTG_HS_DAINTMSK 0x81C OTG_HS_DVBUSDIS 0x828 OTG_HS_DVBUSPULSE 0x82C OTG_HS device IN endpoint common interrupt mask register (OTG_HS_DIEPMSK) on page 1221 OTG_HS device OUT endpoint common interrupt mask register (OTG_HS_DOEPMSK) on page 1222 OTG_HS device all endpoints interrupt register (OTG_HS_DAINT) on page 1223 OTG_HS all endpoints interrupt mask register (OTG_HS_DAINTMSK) on page 1223 OTG_HS device VBUS discharge time register (OTG_HS_DVBUSDIS) on page 1224 OTG_HS device VBUS pulsing time register (OTG_HS_DVBUSPULSE) on page 1224
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Digital-to-analog converter (DAC) R
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Digital camera interface (DCMI) RM0
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Cryptographic processor (CRYP) RM00
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 window
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 33.15.3
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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