RM0090: Reference manual - STMicroelectronics

RM0090 USB on-the-go high-speed (OTG_HS)
bandwidth transfers, the OTG_HS host performs consecutive write operations up
to MC times.
c) The OTG_HS host attempts to send an IN token at the beginning of the next (odd)
frame/micro-frame.
d) As soon the packet is received and written to the receive FIFO, the OTG_HS host
generates a CHH interrupt.
e) In response to the CHH interrupt, reinitialize the channel for the next transfer.
● Bulk and control OUT/SETUP split transactions in DMA mode
The sequence of operations in (channel x) is as follows:
a) Initialize and enable channel x for start split as explained in Section : Channel
initialization.
b) The OTG_HS host starts fetching the first packet as soon the channel is enabled
and writes the OUT request along with the last DWORD fetch.
c) After successfully transmitting start split, the OTG_HS host generates the CHH
interrupt.
d) In response to the CHH interrupt, set the COMPLSPLT bit in HCSPLT1 to send the
complete split.
e) After successfully transmitting complete split, the OTG_HS host generates the
CHH interrupt.
f) In response to the CHH interrupt, de-allocate the channel.
● Bulk/Control IN split transactions in DMA mode
The sequence of operations (channel x) is as follows:
a) Initialize and enable channel x as explained in Section : Channel initialization.
b) The OTG_HS host writes the start split request to the nonperiodic request after
getting the grant from the arbiter. The OTG_HS host masks the channel x
internally for the arbitration after writing the request.
c) As soon as the IN token is transmitted, the OTG_HS host generates the CHH
interrupt.
d) In response to the CHH interrupt, set the COMPLSPLT bit in HCSPLT2 and reenable
the channel to send the complete split token. This unmasks channel x for
arbitration.
e) The OTG_HS host writes the complete split request to the nonperiodic request
after receiving the grant from the arbiter.
f) The OTG_HS host starts writing the packet to the system memory after receiving
the packet successfully.
g) As soon as the received packet is written to the system memory, the OTG_HS
host generates a CHH interrupt.
h) In response to the CHH interrupt, de-allocate the channel.
● Interrupt OUT split transactions in DMA mode
The sequence of operations in (channel x) is as follows:
a) Initialize and enable channel 1 for start split as explained in Section : Channel
initialization. The application must set the ODDFRM bit in HCCHAR1.
b) The HS_OTG host starts reading the packet.
c) The HS_OTG host attempts to send the start split transaction.
d) After successfully transmitting the start split, the OTG_HS host generates the
Doc ID 018909 Rev 3 1284/1416