RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> USB on-the-go full-speed (OTG_FS) Bits 23:22 Reserved, must be kept at reset value. Bit 21 IPXFRM: Incomplete periodic transfer mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in host mode. IISOOXFRM: Incomplete isochronous OUT transfer mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 20 IISOIXFRM: Incomplete isochronous IN transfer mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 19 OEPINT: OUT endpoints interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 18 IEPINT: IN endpoints interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 17 EPMISM: Endpoint mismatch interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 16 Reserved, must be kept at reset value. Bit 15 EOPFM: End of periodic frame interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 14 ISOODRPM: Isochronous OUT packet dropped interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 13 ENUMDNEM: Enumeration done mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 12 USBRST: USB reset mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Doc ID 018909 Rev 3 1060/1416
USB on-the-go full-speed (OTG_FS) <strong>RM0090</strong> Bit 11 USBSUSPM: USB suspend mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 10 ESUSPM: Early suspend mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bits 9:8 Reserved, must be kept at reset value. Bit 7 GONAKEFFM: Global OUT NAK effective mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 6 GINAKEFFM: Global non-periodic IN NAK effective mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 5 NPTXFEM: Non-periodic TxFIFO empty mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in Host mode. Bit 4 RXFLVLM: Receive FIFO non-empty mask 0: Masked interrupt 1: Unmasked interrupt Note: Accessible in both device and host modes. Bit 3 SOFM: Start of frame mask 0: Masked interrupt 1: Unmasked interrupt Note: Accessible in both device and host modes. Bit 2 OTGINT: OTG interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Accessible in both device and host modes. Bit 1 MMISM: Mode mismatch interrupt mask 0: Masked interrupt 1: Unmasked interrupt Note: Accessible in both device and host modes. Bit 0 Reserved, must be kept at reset value. 1061/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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Reset and clock control for (RCC) R
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 Bit 3
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Note: No
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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