RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Universal synchronous asynchronous receiver transmitter (USART) Through these pins, serial data is transmitted and received in normal USART mode as frames comprising: ● An Idle Line prior to transmission or reception ● A start bit ● A data word (8 or 9 bits) least significant bit first ● 0.5,1, 1.5, 2 Stop bits indicating that the frame is complete ● This interface uses a fractional baud rate generator - with a 12-bit mantissa and 4-bit fraction ● A status register (USART_SR) ● Data Register (USART_DR) ● A baud rate register (USART_BRR) - 12-bit mantissa and 4-bit fraction. ● A Guardtime Register (USART_GTPR) in case of Smartcard mode. Refer to Section 26.6: USART registers on page 778 for the definitions of each bit. The following pin is required to interface in synchronous mode: ● SCLK: Transmitter clock output. This pin outputs the transmitter data clock for synchronous transmission corresponding to SPI master mode (no clock pulses on start bit and stop bit, and a software option to send a clock pulse on the last data bit). In parallel data can be received synchronously on RX. This can be used to control peripherals that have shift registers (e.g. LCD drivers). The clock phase and polarity are software programmable. In smartcard mode, SCLK can provide the clock to the smartcard. The following pins are required in Hardware flow control mode: ● nCTS: Clear To Send blocks the data transmission at the end of the current transfer when high ● nRTS: Request to send indicates that the USART is ready to receive a data (when low). Doc ID 018909 Rev 3 740/1416
Universal synchronous asynchronous receiver transmitter (USART) <strong>RM0090</strong> Figure 245. USART block diagram TX RX SW_RX nRTS nCTS IrDA SIR ENDEC block Hardware flow controller PWDATA CR3 Transmit data register (TDR) USART interrupt control Write (CPU or DMA) Transmit Shift Register DMAT DMAR SCEN NACK HD IRLP IREN Transmit control CR2 CR1 TXEIE TCIE RXNE IDLE IE IE Transmitter clock / [8 x (2 - OVER8)] SAMPLING DIVIDER USART Address f PCLKx(x=1,2) Wakeup unit RE RWU SBK Read (CPU or DMA) 741/1416 Doc ID 018909 Rev 3 TE CR1 OVER8 /USARTDIV USARTDIV = DIV_Mantissa + (DIV_Fraction / 8 × (2 – OVER8)) GTPR GT TE RE (Data register) DR Receive data register (RDR) Receive Shift Register PSC CR2 LINE STOP[1:0] CKEN CPOL CPHA LBCL Receiver control CR1 UE M WAKE PCE PS PEIE CTS LBD Receiver clock SR TXETC RXNEIDLEORE NF FE USART_BRR Transmitter rate control DIV_Mantissa DIV_Fraction 15 4 0 Receiver rate control Conventional baud rate generator PRDATA SCLK control SCLK PE ai16099
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 The as
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Real-time clock (RTC) RM0090 23.3.5
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Real-time clock (RTC) RM0090 23.6 R
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Real-time clock (RTC) RM0090 Bit 3
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Serial peripheral interface (SPI) R
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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