RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> USB on-the-go full-speed (OTG_FS) Table 175. OTG_FS register map and reset values (continued) Offset Register 31 0xB48 0xB68 0x910 0x930 0x950 0x970 0xB10 0xB30 0xB50 0xB70 0xE00 OTG_FS_DOEP INT2 Reserved Reset value 0 0 0 0 0 OTG_FS_DOEP INT3 Reserved Reset value 0 0 0 0 0 OTG_FS_DIEP TSIZ0 Reserved PKTC NT Reserved XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 OTG_FS_DIEP TSIZ1 MCNT PKTCNT XFRSIZ Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_DIEP TSIZ2 Reserved MCNT PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_DIEP TSIZ3 Reserved MCNT PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_DOEP TSIZ0 Reserved STUP CNT Reserved Refer to Table 2 on page 53 for the register boundary addresses. PKTCNT Reserved Reserved B2BSTUP Reserved B2BSTUP Reserved OTEPDIS Reserved OTEPDIS Doc ID 018909 Rev 3 1108/1416 STUP STUP XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 OTG_FS_DOEP TSIZ1 Reserved RXDPID/ STUPCNT PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_DOEP TSIZ2 Reserved RXDPID/ STUPCNT PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_DOEP TSIZ3 Reserved RXDPID/ STUPCNT PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_FS_PCG CCTL Reserved Reset value 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PHYSUSP Reserved Reserved EPDISD Reserved EPDISD XFRC XFRC GATEHCLK STPPCLK
USB on-the-go full-speed (OTG_FS) <strong>RM0090</strong> 30.17 OTG_FS programming model 30.17.1 Core initialization The application must perform the core initialization sequence. If the cable is connected during power-up, the current mode of operation bit in the OTG_FS_GINTSTS (CMOD bit in OTG_FS_GINTSTS) reflects the mode. The OTG_FS controller enters host mode when an “A” plug is connected or device mode when a “B” plug is connected. This section explains the initialization of the OTG_FS controller after power-on. The application must follow the initialization sequence irrespective of host or device mode operation. All core global registers are initialized according to the core’s configuration: 1. Program the following fields in the OTG_FS_GAHBCFG register: – Global interrupt mask bit GINTMSK = 1 – RxFIFO non-empty (RXFLVL bit in OTG_FS_GINTSTS) – Periodic TxFIFO empty level 2. Program the following fields in the OTG_FS_GUSBCFG register: – HNP capable bit – SRP capable bit – FS timeout calibration field – USB turnaround time field 3. The software must unmask the following bits in the OTG_FS_GINTMSK register: OTG interrupt mask Mode mismatch interrupt mask 4. The software can read the CMOD bit in OTG_FS_GINTSTS to determine whether the OTG_FS controller is operating in host or device mode. 1109/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.4 DMA
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 Table
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 31 30 29
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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