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RM0090: Reference manual - STMicroelectronics

RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> USB on-the-go high-speed (OTG_HS)<br />

● Isochronous IN transactions<br />

The assumptions are:<br />

– The application is attempting to receive one packet (up to 1 maximum packet size)<br />

in every frame starting with the next odd frame (transfer size = 1 024 bytes).<br />

– The receive FIFO can hold at least one maximum-packet-size packet and two<br />

status DWORDs per packet (1 031 bytes).<br />

– Periodic request queue depth = 4.<br />

The sequence of operations is as follows:<br />

a) Initialize channel 2. The application must set the ODDFRM bit in<br />

OTG_HS_HCCHAR2.<br />

b) Set the CHENA bit in OTG_HS_HCCHAR2 to write an IN request to the periodic<br />

request queue. For a high-bandwidth isochronous transfer, the application must<br />

write the OTG_HS_HCCHAR2 register MCNT (maximum number of expected<br />

packets in the next frame times) before switching to another channel.<br />

c) The OTG_HS host writes an IN request to the periodic request queue for each<br />

OTG_HS_HCCHAR2 register write with the CHENA bit set.<br />

d) The OTG_HS host attempts to send an IN token in the next odd frame.<br />

e) As soon as the IN packet is received and written to the receive FIFO, the OTG_HS<br />

host generates an RXFLVL interrupt.<br />

f) In response to the RXFLVL interrupt, read the received packet status to determine<br />

the number of bytes received, then read the receive FIFO accordingly. The<br />

application must mask the RXFLVL interrupt before reading the receive FIFO, and<br />

unmask it after reading the entire packet.<br />

g) The core generates an RXFLVL interrupt for the transfer completion status entry in<br />

the receive FIFO. This time, the application must read and ignore the receive<br />

packet status when the receive packet status is not an IN data packet (PKTSTS bit<br />

in OTG_HS_GRXSTSR ≠ 0b0010).<br />

h) The core generates an XFRC interrupt as soon as the receive packet status is<br />

read.<br />

i) In response to the XFRC interrupt, read the PKTCNT field in OTG_HS_HCTSIZ2.<br />

If PKTCNT≠ 0 in OTG_HS_HCTSIZ2, disable the channel before re-initializing the<br />

channel for the next transfer, if any. If PKTCNT = 0 in OTG_HS_HCTSIZ2,<br />

reinitialize the channel for the next transfer. This time, the application must reset<br />

the ODDFRM bit in OTG_HS_HCCHAR2.<br />

● Selecting the queue depth<br />

Choose the periodic and nonperiodic request queue depths carefully to match the<br />

number of periodic/nonperiodic endpoints accessed.<br />

The nonperiodic request queue depth affects the performance of nonperiodic transfers.<br />

The deeper the queue (along with sufficient FIFO size), the more often the core is able<br />

to pipeline nonperiodic transfers. If the queue size is small, the core is able to put in<br />

new requests only when the queue space is freed up.<br />

The core’s periodic request queue depth is critical to perform periodic transfers as<br />

scheduled. Select the periodic queue depth, based on the number of periodic transfers<br />

scheduled in a micro-frame. In Slave mode, however, the application must also take<br />

into account the disable entry that must be put into the queue. So, if there are two<br />

nonhigh-bandwidth periodic endpoints, the periodic request queue depth must be at<br />

least 4. If at least one high-bandwidth endpoint is supported, the queue depth must be<br />

Doc ID 018909 Rev 3 1280/1416

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