RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> USB on-the-go full-speed (OTG_FS) ● Isochronous OUT transactions A typical isochronous OUT operation is shown in Figure 371. The assumptions are: – The application is attempting to send one packet every frame (up to 1 maximum packet size), starting with an odd frame. (transfer size = 1 024 bytes). – The periodic transmit FIFO can hold one packet (1 KB). – Periodic request queue depth = 4. The sequence of operations is as follows: a) Initialize and enable channel 1. The application must set the ODDFRM bit in OTG_FS_HCCHAR1. b) Write the first packet for channel 1. c) Along with the last Word write of each packet, the OTG_FS host writes an entry to the periodic request queue. d) The OTG_FS host attempts to send the OUT token in the next frame (odd). e) The OTG_FS host generates the XFRC interrupt as soon as the last packet is transmitted successfully. f) In response to the XFRC interrupt, reinitialize the channel for the next transfer. g) Handling non-ACK responses Doc ID 018909 Rev 3 1124/1416
USB on-the-go full-speed (OTG_FS) <strong>RM0090</strong> Figure 371. Normal isochronous OUT/IN transactions init_reg(ch_2) set_ch_en (ch_2) read_rx_sts read_rx_fifo read_rx_sts init_reg(ch_2) set_ch_en (ch_2) ● Interrupt service routine for isochronous OUT/IN transactions Code sample: Isochronous OUT Unmask (FRMOR/XFRC) if (XFRC) { De-allocate Channel } else if (FRMOR) { Unmask CHH Disable Channel } 1125/1416 Doc ID 018909 Rev 3 1 1 2 2 6 6 Application AHB Host USB Device init_reg(ch_1) write_tx_fifo (ch_1) write_tx_fifo (ch_1) 1 MPS 1 MPS RXFLVL interrupt 1 MPS 7 8 9 init_reg(ch_1) init_reg(ch_1) write_tx_fifo (ch_1) XFRC interrupt RXFLVL interrupt XFRC interrupt XFRC interrupt 1 MPS 3 5 3 5 ch_1 ch_2 ch_1 ch_2 4 4 Periodic Request Queue Assume that this queue can hold 4 entries. OUT DATA0 M PS ACK IN DATA0 ACK OUT DATA1 MPS ACK IN DATA1 Odd (micro) frame Even (micro) frame ai15676
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 9.5.5 D
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Interrupts and events RM0090 Table
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Debug support (DBG) RM0090 33 Debug
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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