RM0090: Reference manual - STMicroelectronics

RM0090 Advanced-control timers (TIM1&TIM8)
14.3.5 Capture/compare channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 97 to Figure 100 give an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).
Figure 97. Capture/compare channel (example: channel 1 input stage)
TI1
f DTS
filter
downcounter
ICF[3:0]
TIMx_CCMR1
Edge
Detector
TI1F_Rising
TI1F_Falling
CC1P/CC1NP
TIMx_CCER
(from channel 2)
The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
Figure 98. Capture/compare channel 1 main circuit
read CCR1H S
read CCR1L
R
CC1S[1]
CC1S[0]
IC1PS
CC1E
CC1G
TIM1_EGR
read_in_progress
input
mode
TI1F
TI2F_rising
(from channel 2)
TI2F_falling
Capture/compare preload register
capture_transfer
Capture/compare shadow register
capture
APB Bus
MCU-peripheral interface
high
(if 16-bit)
8 8
Counter
low
0
1
0
1
TI1FP1
TI1F_ED
TI2FP1
compare_transfer
to the slave mode controller
ICPS[1:0]
divider
/1, /2, /4, /8
Doc ID 018909 Rev 3 366/1416
01
10
TRC
(from slave mode
controller)
11
comparator
CC1S[1:0]
write_in_progress
output
mode
IC1
TIMx_CCMR1
CNT>CCR1
CNT=CCR1
S
R
CC1E
IC1PS
TIMx_CCER
write CCR1H
write CCR1L
CC1S[1]
CC1S[0]
OC1PE
OC1PE
UEV
(from time
base unit)
TIM1_CCMR1