RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Cryptographic processor (CRYP) Table 91. CRYP register map and reset values for STM32F42x and STM32F43x (continued) Register name Offset reset value CRYP_CSGCMCC M4R Register size 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x60 CRYP_CSGCMCCM4R Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x64 CRYP_CSGCMCC M5R CRYP_CSGCMCCM5R Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x68 CRYP_CSGCMCC M6R CRYP_CSGCMCCM6R Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x6C CRYP_CSGCMCC M7R CRYP_CSGCMCCM7R Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x70 CRYP_CSGCM0R Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCM0R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x74 CRYP_CSGCM1R Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCM1R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x78 CRYP_CSGCM2R Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCM2R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x7C CRYP_CSGCM3R Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCM3R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x80 CRYP_CSGCM4R Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCM4R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x84 CRYP_CSGCM5R CRYP_CSGCM5R Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x88 CRYP_CSGCM6R Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCM6R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x8C CRYP_CSGCM7R Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYP_CSGCM7R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRefer to Table 2 on page 53 for the register boundary addresses. Doc ID 018909 Rev 3 588/1416
Random number generator (RNG) <strong>RM0090</strong> 21 Random number generator (RNG) This section applies to the whole STM32F4xx family, unless otherwise specified. 21.1 RNG introduction The RNG processor is a random number generator, based on a continuous analog noise, that provides a random 32-bit value to the host when read. The RNG passed the FIPS PUB 140-2 (2001 October 10) tests with a success ratio of 99%. 21.2 RNG main features ● It delivers 32-bit random numbers, produced by an analog generator ● 40 periods of the PLL48CLK clock signal between two consecutive random numbers ● Monitoring of the RNG entropy to flag abnormal behavior (generation of stable values, or of a stable sequence of values) ● It can be disabled to reduce power-consumption 21.3 RNG functional description Figure 217 shows the RNG block diagram. Figure 217. Block diagram Control register RNG _CR RNG_CLK Status register RNG _SR 32-bit AHB bus Clock checker & fault detector The random number generator implements an analog circuit. This circuit generates seeds that feed a linear feedback shift register (RNG_LFSR) in order to produce 32-bit random numbers. The analog circuit is made of several ring oscillators whose outputs are XORed to generate the seeds. The RNG_LFSR is clocked by a dedicated clock (PLL48CLK) at a constant frequency, so that the quality of the random number is independent of the HCLK frequency. 589/1416 Doc ID 018909 Rev 3 RNG_DR LFSR Analog seed data register feed a Linear Feedback Shift Register ai16080
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.4 DMA
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Basic timers (TIM6&TIM7) RM0090 17.
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Debug support (DBG) RM0090 33 Debug
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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RM0090: Reference manual - STMicroelectronics

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