RM0090: Reference manual - STMicroelectronics

USB on-the-go high-speed (OTG_HS) RM0090
OTG_HS device IN endpoint common interrupt mask register
(OTG_HS_DIEPMSK)
Address offset: 0x810
Reset value: 0x0000 0000
This register works with each of the Device IN endpoint interrupt (OTG_HS_DIEPINTx)
registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt
for a specific status in the OTG_HS_DIEPINTx register can be masked by writing to the
corresponding bit in this register. Status bits are masked by default.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved BIM
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 BIM: BNA interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bit 8 TXFURM: FIFO underrun mask
0: Masked interrupt
1: Unmasked interrupt
Bit 7 Reserved, must be kept at reset value.
Bit 6 INEPNEM: IN endpoint NAK effective mask
0: Masked interrupt
1: Unmasked interrupt
Bit 5 INEPNMM: IN token received with EP mismatch mask
0: Masked interrupt
1: Unmasked interrupt
Bit 4 ITTXFEMSK: IN token received when TxFIFO empty mask
0: Masked interrupt
1: Unmasked interrupt
Bit 3 TOM: Timeout condition mask (nonisochronous endpoints)
0: Masked interrupt
1: Unmasked interrupt
Bit 2 Reserved, must be kept at reset value.
Bit 1 EPDM: Endpoint disabled interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bit 0 XFRCM: Transfer completed interrupt mask
0: Masked interrupt
1: Unmasked interrupt
1221/1416 Doc ID 018909 Rev 3
TXFURM
Reserved
INEPNEM
INEPNMM
ITTXFEMSK
TOM
Reserved
EPDM
XFRCM
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