RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Interrupts and events Table 45. External interrupt/event controller register map and reset values Offset Register 31 0x0C 0x10 0x14 EXTI_FTSR Reserved TR[22:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI_SWIER Reserved SWIER[22:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI_PR 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PR[22:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Table 2 on page 53 for the register boundary addresses. Doc ID 018909 Rev 3 262/1416
Analog-to-digital converter (ADC) <strong>RM0090</strong> 11 Analog-to-digital converter (ADC) This section applies to the whole STM32F4xx family, unless otherwise specified. 11.1 ADC introduction The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19 multiplexed channels allowing it to measure signals from 16 external sources, two internal sources, and the VBAT channel. The A/D conversion of the channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored into a leftor right-aligned 16-bit data register. The analog watchdog feature allows the application to detect if the input voltage goes beyond the user-defined, higher or lower thresholds. 11.2 ADC main features ● 12-bit, 10-bit, 8-bit or 6-bit configurable resolution ● Interrupt generation at the end of conversion, end of injected conversion, and in case of analog watchdog or overrun events ● Single and continuous conversion modes ● Scan mode for automatic conversion of channel 0 to channel ‘n’ ● Data alignment with in-built data coherency ● Channel-wise programmable sampling time ● External trigger option with configurable polarity for both regular and injected conversions ● Discontinuous mode ● Dual/Triple mode (on devices with 2 ADCs or more) ● Configurable DMA data storage in Dual/Triple ADC mode ● Configurable delay between conversions in Dual/Triple interleaved mode ● ADC conversion type (refer to the datasheets) ● ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at slower speed ● ADC input range: V REF– ≤ V IN ≤ V REF+ ● DMA request generation during regular channel conversion Figure 34 shows the block diagram of the ADC. Note: V REF– , if available (depending on package), must be tied to V SSA . 11.3 ADC functional description Figure 34 shows a single ADC block diagram and Table 46 gives the ADC pin description. 263/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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Memory and bus architecture RM0090
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Window watchdog (WWDG) RM0090 19 Wi
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Debug support (DBG) RM0090 33 Debug
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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