RM0090: Reference manual - STMicroelectronics

USB on-the-go high-speed (OTG_HS) RM0090
31.12.1 CSR memory map
The host and peripheral mode registers occupy different addresses. All registers are
implemented in the AHB clock domain.
Figure 383. CSR memory map
0000h
0400h
0800h
0E00h
1000h
2000h
3000h
2 0000h
3 FFFFh
1. x = 5 in peripheral mode and x = 11 in host mode.
Core global CSRs (1 Kbyte)
Host mode CSRs (1 Kbyte)
Device mode CSRs (1.5 Kbyte)
Power and clock gating CSRs (0.5 Kbyte)
Device EP 0/Host channel 0 FIFO (4 Kbyte)
Device EP1/Host channel 1 FIFO (4 Kbyte)
Device EP (x – 1) (1) /Host channel (x – 1) (1) FIFO (4 Kbyte)
Device EP x (1) /Host channel x (1) FIFO (4 Kbyte)
Reserved
Direct access to data FIFO RAM
for debugging (128 Kbyte)
Global CSR map
These registers are available in both host and peripheral modes.
Table 176. Core global control and status registers (CSRs)
Acronym
Address
offset
Register name
1175/1416 Doc ID 018909 Rev 3
DFIFO
push/pop
to this region
DFIFO
debug read/
write to this
region
ai15615b
OTG_HS_GOTGCTL 0x000 OTG_HS control and status register (OTG_HS_GOTGCTL) on page 1180
OTG_HS_GOTGINT 0x004 OTG_HS interrupt register (OTG_HS_GOTGINT) on page 1182
OTG_HS_GAHBCFG 0x008 OTG_HS AHB configuration register (OTG_HS_GAHBCFG) on page 1183
OTG_HS_GUSBCFG 0x00C OTG_HS USB configuration register (OTG_HS_GUSBCFG) on page 1184
OTG_HS_GRSTCTL 0x010 OTG_HS reset register (OTG_HS_GRSTCTL) on page 1187