RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> USB on-the-go full-speed (OTG_FS) SETUP transaction operates in the same way but has only one packet. The assumptions are: – The application is attempting to send two maximum-packet-size packets (transfer size = 1, 024 bytes). – The non-periodic transmit FIFO can hold two packets (128 bytes for FS). – The non-periodic request queue depth = 4. ● Normal bulk and control OUT/SETUP operations The sequence of operations in (channel 1) is as follows: a) Initialize channel 1 b) Write the first packet for channel 1 c) Along with the last Word write, the core writes an entry to the non-periodic request queue d) As soon as the non-periodic queue becomes non-empty, the core attempts to send an OUT token in the current frame e) Write the second (last) packet for channel 1 f) The core generates the XFRC interrupt as soon as the last transaction is completed successfully g) In response to the XFRC interrupt, de-allocate the channel for other transfers h) Handling non-ACK responses Doc ID 018909 Rev 3 1114/1416
USB on-the-go full-speed (OTG_FS) <strong>RM0090</strong> Figure 368. Normal bulk/control OUT/SETUP and bulk/control IN transactions init_reg(ch_2) set_ch_en (ch_2) set_ch_en (ch_2) set_ch_en (ch_2) read_rx_sts read_rx_fifo set_ch_en (ch_2) read_rx_stsre ad_rx_fifo read_rx_sts Disable (ch_2) De-allocate (ch_2) The channel-specific interrupt service routine for bulk and control OUT/SETUP transactions is shown in the following code samples. ● Interrupt service routine for bulk/control OUT/SETUP and bulk/control IN transactions a) Bulk/Control OUT/SETUP Unmask (NAK/TXERR/STALL/XFRC) if (XFRC) { Reset Error Count Mask ACK 1115/1416 Doc ID 018909 Rev 3 1 1 2 2 5 5 7 7 9 Application AHB Host USB Device init_reg(ch_1) write_tx_fifo (ch_1) write_tx_fifo (ch_1) De-allocate (ch_1) 1 MPS 1 MPS 1 MPS 1 MPS read_rx_sts 11 10 CHH interrupt r 13 RXFLVL interrupt XFRC interrupt RXFLVL interrupt RXFLVL interrupt XFRC interrupt RXFLVL interrupt 8 6 3 6 12 4 ch_1 ch_2 ch_1 ch_2 3 ch_1 ch_2 ch_2 ch_2 ch_2 4 Non-Periodic Request Queue Assume that this queue can hold 4 entries. OUT DATA0 MPS ACK IN DATA0 ACK OUT DATA1 MPS ACK IN DATA1 ACK ai15675
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 Bit 3
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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