RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Controller area network (bxCAN) 24.9.5 bxCAN register map Refer to Table 2 on page 53 for the register boundary addresses. The registers from offset 0x200 to 31C are present only in CAN1. Table 100. bxCAN register map and reset values Offset Register 31 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020- 0x17F 0x180 0x184 0x188 0x18C 0x190 CAN_MCR 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DBF RESET Reserved Reset value 1 0 0 0 0 0 0 0 1 0 CAN_MSR Reserved RX SAMP RXM TXM TTCM ABOM AWUM NART Reserved Reset value 1 1 0 0 0 0 0 1 0 CAN_TSR LOW[2:0] TME[2:0] CODE[1:0] ABRQ2 Reserved TERR2 ALST2 TXOK2 RQCP2 ABRQ1 Reserved TERR1 ALST1 TXOK1 RQCP1 SLAKI WKUI RFLM TXFP ERRI SLAK SLEEP INRQ Doc ID 018909 Rev 3 700/1416 ABRQ0 Reserved Reset value 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_RF0R Reserved Reset value 0 0 0 0 0 CAN_RF1R Reserved Reset value 0 0 0 0 0 CAN_IER Reserved SLKIE WKUIE ERRIE Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_ESR REC[7:0] TEC[7:0] LECIE BOFIE Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN_BTR SILM LBKM Reserved SJW[1:0] Reserved TS2[2:0] TS1[3:0] Reserved EPVIE EWGIE Reserved FOVIE1 RFOM0 FOVR0 RFOM1 FOVR1 FFIE1 FMPIE1 LEC[2:0] BRP[9:0] Reset value 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 Reserved CAN_TI0R STID[10:0]/EXID[28:18] EXID[17:0] TERR0 ALST0 FULL0 FULL1 Reserved Reserved FOVIE0 FFIE0 Reserved BOFF INAK TXOK0 RQCP0 FMP0[1:0] FMP1[1:0] FMPIE0 TMEIE EPVF EWGF IDE RTR TXRQ Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 CAN_TDT0R TIME[15:0] Reserved TGT Reserved DLC[3:0] Reset value x x x x x x x x x x x x x x x x x x x x x CAN_TDL0R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x CAN_TDH0R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x CAN_TI1R STID[10:0]/EXID[28:18] EXID[17:0] IDE RTR TXRQ Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0
Controller area network (bxCAN) <strong>RM0090</strong> Table 100. bxCAN register map and reset values (continued) Offset Register 31 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0- 0x1FF 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAN_TDT1R TIME[15:0] 701/1416 Doc ID 018909 Rev 3 Reserved TGT Reserved DLC[3:0] Reset value x x x x x x x x x x x x x x x x x x x x x CAN_TDL1R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x CAN_TDH1R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x CAN_TI2R STID[10:0]/EXID[28:18] EXID[17:0] IDE RTR TXRQ Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 CAN_TDT2R TIME[15:0] Reserved TGT Reserved DLC[3:0] Reset value x x x x x x x x x x x x x x x x x x x x x CAN_TDL2R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x CAN_TDH2R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x CAN_RI0R STID[10:0]/EXID[28:18] EXID[17:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x CAN_RDT0R TIME[15:0] FMI[7:0] Reserved IDE RTR DLC[3:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x CAN_RDL0R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x CAN_RDH0R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x CAN_RI1R STID[10:0]/EXID[28:18] EXID[17:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x CAN_RDT1R TIME[15:0] FMI[7:0] Reserved IDE RTR DLC[3:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x CAN_RDL1R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x CAN_RDH1R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reserved Reserved Reserved
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 Safe RTC
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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Flexible static memory controller (
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Table 22
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 33.11 Ca
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 33.15.3
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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