RM0090: Reference manual - STMicroelectronics

Advanced-control timers (TIM1&TIM8) RM0090
Figure 89. Counter timing diagram, update event with ARPE=1 (counter underflow)
Figure 90. Counter timing diagram, Update event with ARPE=1 (counter overflow)
14.3.3 Repetition counter
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Section 14.3.1: Time-base unit describes how the update event (UEV) is generated with
respect to the counter overflows/underflows. It is actually generated only when the repetition
counter has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx
capture/compare registers in compare mode) every N+1 counter overflows or underflows,
where N is the value in the TIMx_RCR repetition counter register.
361/1416 Doc ID 018909 Rev 3
06
05 04 03 02 01 00 01 02 03 04 05 06 07
Auto-reload preload register FD 36
Write a new value in TIMx_ARR
Auto-reload active register FD 36
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
F7
F8 F9 FA FB FC 36 35 34 33 32 31 30 2F
Auto-reload preload register FD 36
Write a new value in TIMx_ARR
Auto-reload active register FD 36