RM0090: Reference manual - STMicroelectronics

RM0090 USB on-the-go full-speed (OTG_FS)
Table 172. Data FIFO (DFIFO) access register map
Power and clock gating CSR map
There is a single register for power and clock gating. It is available in both host and device
modes.
30.16.2 OTG_FS global registers
FIFO access register section Address range Access
Device IN Endpoint 0/Host OUT Channel 0: DFIFO Write Access
Device OUT Endpoint 0/Host IN Channel 0: DFIFO Read Access
Device IN Endpoint 1/Host OUT Channel 1: DFIFO Write Access
Device OUT Endpoint 1/Host IN Channel 1: DFIFO Read Access
These registers are available in both host and device modes, and do not need to be
reprogrammed when switching between these modes.
Bit values in the register descriptions are expressed in binary unless otherwise specified.
OTG_FS control and status register (OTG_FS_GOTGCTL)
0x1000–0x1FFC
0x2000–0x2FFC
... ... ...
Device IN Endpoint x (1) /Host OUT Channel x (1) : DFIFO Write Access
Device OUT Endpoint x (1) /Host IN Channel x (1) : DFIFO Read Access
1. Where x is 3 in device mode and 7 in host mode.
Table 173. Power and clock gating control and status registers
Address offset: 0x000
Reset value: 0x0000 0800
The OTG_FS_GOTGCTL register controls the behavior and reflects the status of the OTG
function of the core.
Doc ID 018909 Rev 3 1046/1416
w
r
w
r
0xX000h–0xXFFCh w
r
Register name Acronym Offset address: 0xE00–0xFFF
Power and clock gating control register PCGCR 0xE00-0xE04
Reserved 0xE05–0xFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved BSVLD
ASVLD
DBCT
CIDSTS
Reserved
DHNPEN
HSHNPEN
HNPRQ
HNGSCS
Reserved SRQ
r r r r rw rw rw r rw r
SRQSCS