RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Embedded Flash memory interface Table 14. OTP area organization Block [128:96] [95:64] [63:32] [31:0] Address byte 0 15 Lock block The OTP area is divided into 16 OTP data blocks of 32 bytes and one lock OTP block of 16 bytes. The OTP data and lock blocks cannot be erased. The lock block contains 16 bytes LOCKBi (0 ≤ i ≤ 15) to lock the corresponding OTP data block (blocks 0 to 15). Each OTP data block can be programmed until the value 0x00 is programmed in the corresponding OTP lock byte. The lock bytes must only contain 0x00 and 0xFF values, otherwise the OTP bytes might not be taken into account correctly. 3.8 Flash interface registers OTP15 OTP15 OTP15 OTP15 0x1FFF 79E0 OTP15 OTP15 OTP15 OTP15 0x1FFF 79F0 LOCKB15 ... LOCKB12 LOCKB11 ... LOCKB8 LOCKB7 ... LOCKB4 3.8.1 Flash access control register (FLASH_ACR) LOCKB3 ... LOCKB0 0x1FFF 7A00 The Flash access control register is used to enable/disable the acceleration features and control the Flash memory access time according to CPU frequency. Address offset: 0x00 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 Reserved 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DCRST rw ICRST w DCEN rw ICEN rw PRFTEN rw Reserved rw LATENCY rw rw Bits 31:11 Reserved, must be kept cleared. Bit 12 DCRST: Data cache reset 0: Data cache is not reset 1: Data cache is reset This bit can be written only when the D cache is disabled. Bit 11 ICRST: Instruction cache reset 0: Instruction cache is not reset 1: Instruction cache is reset This bit can be written only when the I cache is disabled. Bit 10 DCEN: Data cache enable 0: Data cache is disabled 1: Data cache is enabled Bit 9 ICEN: Instruction cache enable 0: Instruction cache is disabled 1: Instruction cache is enabled Doc ID 018909 Rev 3 76/1416
Embedded Flash memory interface <strong>RM0090</strong> Bit 8 PRFTEN: Prefetch enable 0: Prefetch is disabled 1: Prefetch is enabled Bits 7:3 Reserved, must be kept cleared. Bits 2:0 LATENCY: Latency These bits represent the ratio of the CPU clock period to the Flash memory access time. 000: Zero wait state 001: One wait state 010: Two wait states 011: Three wait states 100: Four wait states 101: Five wait states 110: Six wait states 111: Seven wait states 77/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Page 31 and 32: Contents RM0090 33.2 Reference ARM
Page 33 and 34: List of tables RM0090 List of table
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Page 47 and 48: Documentation conventions RM0090 1
Page 49 and 50: Memory and bus architecture RM0090
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Reset and clock control for (RCC) R
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System configuration controller (SY
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Analog-to-digital converter (ADC) R
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 The as
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Real-time clock (RTC) RM0090 23.3.5
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Real-time clock (RTC) RM0090 The fo
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Real-time clock (RTC) RM0090 Sectio
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Real-time clock (RTC) RM0090 Bit 3
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Table 22
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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