RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> General-purpose I/Os (GPIO) 31 Table 31. GPIO register map and reset values (continued) Offset Register 0x08 0x08 0x0C 0x0C 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 GPIOx_OSPEED ER (where x = A..I/ except B) OSPEEDR15[1:0] OSPEEDR14[1:0] OSPEEDR13[1:0] OSPEEDR12[1:0] OSPEEDR11[1:0] Refer to Table 2 on page 53 for the register boundary addresses. OSPEEDR10[1:0] OSPEEDR9[1:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOB_OSPEED ER OSPEEDR15[1:0] OSPEEDR14[1:0] OSPEEDR13[1:0] OSPEEDR12[1:0] OSPEEDR11[1:0] OSPEEDR10[1:0] OSPEEDR9[1:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 GPIOA_PUPDR PUPDR15[1:0] PUPDR14[1:0] PUPDR13[1:0] PUPDR12[1:0] PUPDR11[1:0] PUPDR10[1:0] PUPDR9[1:0] Reset value 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOB_PUPDR PUPDR15[1:0] PUPDR14[1:0] PUPDR13[1:0] PUPDR12[1:0] PUPDR11[1:0] PUPDR10[1:0] PUPDR9[1:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 GPIOx_PUPDR (where x = C..I/) PUPDR15[1:0] PUPDR14[1:0] PUPDR13[1:0] PUPDR12[1:0] PUPDR11[1:0] PUPDR10[1:0] PUPDR9[1:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_IDR (where x = A..I/) Reserved Reset value x x x x x x x x x x x x x x x x GPIOx_ODR (where x = A..I/) Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_BSRR (where x = A..I/) BR15 BR14 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSPEEDR8[1:0] OSPEEDR8[1:0] PUPDR8[1:0] PUPDR8[1:0] PUPDR8[1:0] BR1 BR0 GPIOx_LCKR (where x = A..I/) Reserved LCKK Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_AFRL (where x = A..I/) AFRL7[3:0] AFRL6[3:0] AFRL5[3:0] AFRL4[3:0] AFRL3[3:0] AFRL2[3:0] AFRL1[3:0] AFRL0[3:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_AFRH (where x = A..I/) AFRH15[3:0] AFRH14[3:0] AFRH13[3:0] AFRH12[3:0] AFRH11[3:0] AFRH10[3:0] AFRH9[3:0] AFRH8[3:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OSPEEDR7[1:0] OSPEEDR7[1:0] PUPDR7[1:0] PUPDR7[1:0] PUPDR7[1:0] IDR15 IDR14 ODR15 ODR14 BS15 BS14 LCK15 LCK14 OSPEEDR6[1:0] OSPEEDR6[1:0] PUPDR6[1:0] PUPDR6[1:0] PUPDR6[1:0] IDR13 IDR12 ODR13 ODR12 BS13 BS12 LCK13 LCK12 Doc ID 018909 Rev 3 204/1416 OSPEEDR5[1:0] OSPEEDR5[1:0] PUPDR5[1:0] PUPDR5[1:0] PUPDR5[1:0] IDR11 IDR10 ODR11 ODR10 BS11 BS10 LCK11 LCK10 OSPEEDR4[1:0] OSPEEDR4[1:0] PUPDR4[1:0] PUPDR4[1:0] PUPDR4[1:0] IDR9 IDR8 ODR9 ODR8 BS9 BS8 LCK9 LCK8 OSPEEDR3[1:0] OSPEEDR3[1:0] PUPDR3[1:0] PUPDR3[1:0] PUPDR3[1:0] IDR7 IDR6 ODR7 ODR6 BS7 BS6 LCK7 LCK6 OSPEEDR2[1:0] OSPEEDR2[1:0] PUPDR2[1:0] PUPDR2[1:0] PUPDR2[1:0] IDR5 IDR4 ODR5 ODR4 BS5 BS4 LCK5 LCK4 OSPEEDR1[1:0] OSPEEDR1[1:0] PUPDR1[1:0] PUPDR1[1:0] PUPDR1[1:0] IDR3 IDR2 ODR3 ODR2 BS3 BS2 LCK3 LCK2 OSPEEDR0[1:0] OSPEEDR0[1:0] PUPDR0[1:0] PUPDR0[1:0] PUPDR0[1:0] IDR1 IDR0 ODR1 ODR0 BS1 BS0 LCK1 LCK0
System configuration controller (SYSCFG) <strong>RM0090</strong> 8 System configuration controller (SYSCFG) The system configuration controller is mainly used to remap the memory accessible in the code area, select the Ethernet PHY interface and manage the external interrupt line connection to the GPIOs. This section applies to the whole STM32F4xx family, unless otherwise specified. 8.1 I/O compensation cell By default the I/O compensation cell is not used. However when the I/O output buffer speed is configured in 50 MHz or 100 MHz mode, it is recommended to use the compensation cell for slew rate control on I/O tf(IO)out )/tr(IO)out commutation to reduce the I/O noise on power supply. When the compensation cell is enabled, a READY flag is set to indicate that the compensation cell is ready and can be used. The I/O compensation cell can be used only when the supply voltage ranges from 2.4 to 3.6 V. 8.2 SYSCFG registers 8.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP) This register is used for specific configurations on memory remap: ● Two bits are used to configure the type of memory accessible at address 0x0000 0000. These bits are used to select the physical remap by software and so, bypass the BOOT pins. ● After reset these bits take the value selected by the BOOT pins. When booting from main Flash memory with BOOT pins set to 10 [(BOOT1,BOOT0) = (1,0)] this register takes the value 0x00. When the FSMC is remapped at address 0x0000 0000, only the first two regions of Bank 1 memory controller (Bank1 NOR/PSRAM 1 and NOR/PSRAM 2) can be remapped. In remap mode, the CPU can access the external memory via ICode bus instead of System bus which boosts up the performance. Address offset: 0x00 Reset value: 0x0000 000X (X is the memory mode selected by the BOOT pins ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MEM_MODE Reserved rw rw 205/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 12.4.2 Independent
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 5.4.3 PW
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Flexible static memory controller (
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Table 22
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 33.11 Ca
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 33.15.3
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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