RM0090: Reference manual - STMicroelectronics

Flexible static memory controller (FSMC) RM0090
32.5.4 NOR Flash/PSRAM controller asynchronous transactions
Asynchronous static memories (NOR Flash, SRAM)
● Signals are synchronized by the internal clock HCLK. This clock is not issued to the
memory
● The FSMC always samples the data before de-asserting the chip select signal NE. This
guarantees that the memory data-hold timing constraint is met (chip enable high to
data transition, usually 0 ns min.)
● When extended mode is set, it is possible to mix modes A, B, C and D in read and write
(it is for instance possible to read in mode A and write in mode B).
Mode 1 - SRAM/CRAM
Figure 404. Mode1 read accesses
A[25:0]
NBL[1:0]
NEx
NOE
NWE
D[15:0]
High
1. NBL[1:0] are driven low during read access.
Memory transaction
ADDSET DATAST
HCLK cycles HCLK cycles
1323/1416 Doc ID 018909 Rev 3
data driven
by memory
ai15557