RM0090: Reference manual - STMicroelectronics

Serial peripheral interface (SPI) RM0090
Figure 300. Operations required to receive 0x3478AE
Figure 301. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0
CK
WS
SD
When 16-bit data frame extended to 32-bit channel frame is selected during the I 2 S
configuration phase, Only one access to SPI_DR is required. The 16 remaining bits are
forced by hardware to 0x0000 to extend the data to 32-bit format. In this case it corresponds
to the half-word MSB.
If the data to transmit or the received data are 0x76A3 (0x0000 76A3 extended to 32-bit),
the operation shown in Figure 302 is required.
Figure 302. Example of LSB justified 16-bit extended to 32-bit packet frame
In transmission mode, when TXE is asserted, the application has to write the data to be
transmitted (in this case 0x76A3). The 0x000 field is transmitted first (extension on 32-bit).
TXE is asserted again as soon as the effective data (0x76A3) is sent on SD.
In reception mode, RXNE is asserted as soon as the significant half-word is received (and
not the 0x0000 field).
In this way, more time is provided between two write or read operations to prevent underrun
or overrun conditions.
PCM standard
First read from Data register
conditioned by RXNE = ‘1’
0x0034 0x78AE
Only the 8 LSB bits of the half-word
are significant. Whatever the 8 MSBs,
a field of 0x00 is forced instead
16-bit data
0 forced
Channel left 32-bit
For the PCM standard, there is no need to use channel-side information. The two PCM
modes (short and long frame) are available and configurable using the PCMSYNC bit in
SPI_I2SCFGR.
823/1416 Doc ID 018909 Rev 3
MSB LSB
Only one access to SPI_DR
Second read from Data register
conditioned by RXNE = ‘1’
Transmission Reception
0X76A3
16-bit remaining
Channel right