RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Universal synchronous asynchronous receiver transmitter (USART) 26.6.7 Guard time and prescaler register (USART_GTPR) Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GT[7:0] PSC[7:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value Bits 15:8 GT[7:0]: Guard time value This bit-field gives the Guard time value in terms of number of baud clocks. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. Note: This bit is not available for UART4 & UART5. Bits 7:0 PSC[7:0]: Prescaler value – In IrDA Low-power mode: PSC[7:0] = IrDA Low-Power Baud Rate Used for programming the prescaler for dividing the system clock to achieve the low-power frequency: The source clock is divided by the value given in the register (8 significant bits): 00000000: Reserved - do not program this value 00000001: divides the source clock by 1 00000010: divides the source clock by 2 ... – In normal IrDA mode: PSC must be set to 00000001. – In smartcard mode: PSC[4:0]: Prescaler value Used for programming the prescaler for dividing the system clock to provide the smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: 00000: Reserved - do not program this value 00001: divides the source clock by 2 00010: divides the source clock by 4 00011: divides the source clock by 6 ... Note: 1: Bits [7:5] have no effect if Smartcard mode is used. 2: This bit is not available for UART4 & UART5. Doc ID 018909 Rev 3 788/1416
Universal synchronous asynchronous receiver transmitter (USART) <strong>RM0090</strong> 26.6.8 USART register map The table below gives the USART register map and reset values. Table 121. USART register map and reset values Offset Register 31 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 USART_SR 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Refer to Table 2 on page 53 for the register boundary addresses. 789/1416 Doc ID 018909 Rev 3 Reserved CTS LBD TXE TC RXNE IDLE ORE NF FE PE Reset value 0 0 1 1 0 0 0 0 0 0 USART_DR Reserved DR[8:0] Reset value 0 0 0 0 0 0 0 0 0 USART_BRR Reserved DIV_Mantissa[15:4] DIV_Fraction [3:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART_CR1 Reserved OVER8 Reserved UE M WAKE PCE PS PEIE TXEIE TCIE RXNEIE IDLEIE TE RE Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART_CR2 Reserved LINEN STOP [1:0] CLKEN CPOL CPHA LBCL Reserved LBDIE LBDL Reserved RWU SBK ADD[3:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 USART_CR3 Reserved ONEBIT CTSIE CTSE RTSE DMAT DMAR SCEN NACK HDSEL IRLP IREN EIE Reset value 0 0 0 0 0 0 0 0 0 0 0 0 USART_GTPR Reserved GT[7:0] PSC[7:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 12.4.2 Independent
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 9.5.5 D
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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