RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> General-purpose timers (TIM2 to TIM5) Figure 162. Triggering timer 2 with update of timer 1 CK_INT TIMER1-UEV TIMER1-CNT TIMER2-CNT TIMER2-CEN=CNT_EN TIMER 2-TIF FD FE FF 00 01 Write TIF=0 As in the previous example, you can initialize both counters before starting counting. Figure 163 shows the behavior with the same configuration as in Figure 162 but in trigger mode instead of gated mode (SMS=110 in the TIM2_SMCR register). Figure 163. Triggering timer 2 with Enable of timer 1 CK_INT TIMER1-CEN=CNT_EN TIMER1-CNT_INIT TIMER1-CNT TIMER2-CNT TIMER2-CNT_INIT TIMER2 write CNT TIMER 2-TIF 45 46 47 48 75 00 01 CD 00 E7 E8 E9 EA Write TIF=0 Doc ID 018909 Rev 3 452/1416 02 02
General-purpose timers (TIM2 to TIM5) <strong>RM0090</strong> Using one timer as prescaler for another timer For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Figure 159 for connections. To do this: ● Configure Timer 1 master mode to send its Update Event (UEV) as trigger output (MMS=010 in the TIM1_CR2 register). then it outputs a periodic signal on each counter overflow. ● Configure the Timer 1 period (TIM1_ARR registers). ● Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register). ● Configure Timer 2 in external clock mode 1 (SMS=111 in TIM2_SMCR register). ● Start Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register). ● Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register). Starting 2 timers synchronously in response to an external trigger In this example, we set the enable of timer 1 when its TI1 input rises, and the enable of Timer 2 with the enable of Timer 1. Refer to Figure 159 for connections. To ensure the counters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect to TI1, master with respect to Timer 2): ● Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the TIM1_CR2 register). ● Configure Timer 1 slave mode to get the input trigger from TI1 (TS=100 in the TIM1_SMCR register). ● Configure Timer 1 in trigger mode (SMS=110 in the TIM1_SMCR register). ● Configure the Timer 1 in Master/Slave mode by writing MSM=1 (TIM1_SMCR register). ● Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register). ● Configure Timer 2 in trigger mode (SMS=110 in the TIM2_SMCR register). When a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on the internal clock and both TIF flags are set. Note: In this example both timers are initialized before starting (by setting their respective UG bits). Both counters starts from 0, but you can easily insert an offset between them by writing any of the counter registers (TIMx_CNT). You can see that the master/slave mode insert a delay between CNT_EN and CK_PSC on timer 1. 453/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Page 401 and 402: Advanced-control timers (TIM1&TIM8)
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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