RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> USB on-the-go high-speed (OTG_HS) Table 182. OTG_HS register map and reset values (continued) Offset Register 31 0xB60 0x908 0x928 0x948 0x968 0x988 0x9A8 0x9C8 0x9E8 0xB08 OTG_HS_DOE PCTL3 EPENA EPDIS 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SODDFRM SD0PID/SEVNFRM SNAK CNAK Reserved Stall SNPM EPTYP NAKSTS EONUM/DPID USBAEP Reserved MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DIEPI NT0 Reserved NAK BERR PKTDRPSTS Reserved Doc ID 018909 Rev 3 1254/1416 BNA TXFIFOUDRN TXFE INEPNE Reserved ITTXFE TOC Reset value 0 0 0 0 0 1 0 0 0 0 0 OTG_HS_DIEPI NT1 Reserved NAK BERR PKTDRPSTS Reserved BNA TXFIFOUDRN TXFE INEPNE Reserved ITTXFE TOC Reset value 0 0 0 0 0 1 0 0 0 0 0 OTG_HS_DIEPI NT2 Reserved NAK BERR PKTDRPSTS Reserved BNA TXFIFOUDRN TXFE INEPNE Reserved ITTXFE TOC Reset value 0 0 0 0 0 1 0 0 0 0 0 OTG_HS_DIEPI NT3 Reserved NAK BERR PKTDRPSTS Reserved BNA TXFIFOUDRN TXFE INEPNE Reserved ITTXFE TOC Reset value 0 0 0 0 0 1 0 0 0 0 0 OTG_HS_DIEPI NT4 Reserved NAK BERR PKTDRPSTS Reserved BNA TXFIFOUDRN TXFE INEPNE Reserved ITTXFE TOC Reset value 0 0 0 0 0 1 0 0 0 0 0 OTG_HS_DIEPI NT5 Reserved NAK BERR PKTDRPSTS Reserved BNA TXFIFOUDRN TXFE INEPNE Reserved ITTXFE TOC Reset value 0 0 0 0 0 1 0 0 0 0 0 OTG_HS_DIEPI NT6 Reserved NAK BERR PKTDRPSTS Reserved BNA TXFIFOUDRN TXFE INEPNE Reserved ITTXFE TOC Reset value 0 0 0 0 0 1 0 0 0 0 0 OTG_HS_DIEPI NT7 Reserved NAK BERR PKTDRPSTS Reserved BNA TXFIFOUDRN TXFE INEPNE Reserved ITTXFE TOC Reset value 0 0 0 0 0 1 0 0 0 0 0 OTG_HS_DOE PINT0 Reserved NYET Reserved Reset value 0 0 0 1 0 0 B2BSTUP Reserved OTEPDIS STUP Reserved EPDISD Reserved EPDISD Reserved EPDISD Reserved EPDISD Reserved EPDISD Reserved EPDISD Reserved EPDISD Reserved EPDISD Reserved EPDISD XFRC XFRC XFRC XFRC XFRC XFRC XFRC XFRC XFRC
USB on-the-go high-speed (OTG_HS) <strong>RM0090</strong> Table 182. OTG_HS register map and reset values (continued) Offset Register 31 0xB28 0xB48 0xB68 0xB88 0xBA8 0xBC8 0xBE8 0x910 0x930 0x934 0x93C 0x950 0x954 0x95C 0x970 0x974 0x97C OTG_HS_DOE PINT1 Reserved 1255/1416 Doc ID 018909 Rev 3 NYET Reserved Reset value 0 0 0 0 0 0 OTG_HS_DOE PINT2 Reserved NYET Reserved Reset value 0 0 0 0 0 0 OTG_HS_DOE PINT3 Reserved NYET Reserved Reset value 0 0 0 0 0 0 OTG_HS_DOE PINT4 Reserved NYET Reserved Reset value 0 0 0 0 0 0 OTG_HS_DOE PINT5 Reserved NYET Reserved Reset value 0 0 0 0 0 0 OTG_HS_DOE PINT6 Reserved NYET Reserved Reset value 0 0 0 0 0 0 OTG_HS_DOE PINT7 Reserved NYET Reserved Reset value 0 0 0 0 0 0 OTG_HS_DIEP TSIZ0 Reserved PKTC NT Reserved XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 OTG_HS_DIEP TSIZ1 MCNT PKTCNT XFRSIZ Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DIEP DMA1 DMAADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DIEP DMAB1 DMABADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DIEP TSIZ2 MCNT PKTCNT XFRSIZ Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DIEP DMA2 DMAADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DIEP DMAB2 DMABADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DIEP TSIZ3 MCNT PKTCNT XFRSIZ Reserved 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DIEP DMA3 DMAADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_DIEP DMAB3 DMABADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B2BSTUP Reserved B2BSTUP Reserved B2BSTUP Reserved B2BSTUP Reserved B2BSTUP Reserved B2BSTUP Reserved B2BSTUP Reserved OTEPDIS STUP OTEPDIS STUP OTEPDIS STUP OTEPDIS STUP OTEPDIS STUP OTEPDIS STUP OTEPDIS STUP Reserved EPDISD Reserved EPDISD Reserved EPDISD Reserved EPDISD Reserved EPDISD Reserved EPDISD Reserved EPDISD XFRC XFRC XFRC XFRC XFRC XFRC XFRC
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Cryptographic processor (CRYP) RM00
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 RTC_TR
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 33.11 Ca
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 33.15.3
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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show all

RM0090: Reference manual - STMicroelectronics

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