RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Serial peripheral interface (SPI) In Slave mode (Figure 273: TI mode - Slave mode, single transfer and Figure 274: TI mode - Slave mode, continuous transfer), the SPI baud rate prescaler is used to control the moment when the MISO pin state changes to HiZ. Any baud rate can be used thus allowing to determine this moment with optimal flexibility. However, the baud rate is generally set to the external master clock baud rate. The time for the MISO signal to become HiZ (t release ) depends on internal resynchronizations and on the baud rate value set in through BR[2:0] of SPI_CR1 register. It is given by the formula: tbaud_rate --------------------- + 4× tpclk < trelease < 2 Note: This feature is not available for Motorola SPI communications (FRF bit set to 0). To detect TI frame errors in Slave transmitter only mode by using the Error interrupt (ERRIE = 1), the SPI must be configured in 2-line unidirectional mode by setting BIDIMODE and BIDIOE to 1 in the SPI_CR1 register. When BIDIMODE is set to 0, OVR is set to 1 because the data register is never read and error interrupt are always generated, while when BIDIMODE is set to 1, data are not received and OVR is never set. Figure 273. TI mode - Slave mode, single transfer Figure 274. TI mode - Slave mode, continuous transfer NSS input SCK input MOSI input MISO output NSS input SCK input MOSI input MISO output trigger edge sampling trigger edge edge sampling edge t baud_rate 2 --------------------- + 6× tpclk trigger edge t Release sampling edge DONTCARE MSBIN LSBIN DONTCARE 1 or 0 MSBOUT LSBOUT trigger sampling trigger sampling trigger sampling ai18434 DONTCARE MSBIN LSBIN MSBIN LSBIN DONTCARE 1 or 0 MSBOUT LSBOUT MSBOUT LSBOUT FRAME 1 FRAME 2 ai18435 Doc ID 018909 Rev 3 798/1416
Serial peripheral interface (SPI) <strong>RM0090</strong> 27.3.3 Configuring the SPI in master mode In the master configuration, the serial clock is generated on the SCK pin. Procedure 1. Select the BR[2:0] bits to define the serial clock baud rate (see SPI_CR1 register). 2. Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 272). This step is not required when the TI mode is selected. 3. Set the DFF bit to define 8- or 16-bit data frame format 4. Configure the LSBFIRST bit in the SPI_CR1 register to define the frame format. This step is not required when the TI mode is selected. 5. If the NSS pin is required in input mode, in hardware mode, connect the NSS pin to a high-level signal during the complete byte transmit sequence. In NSS software mode, set the SSM and SSI bits in the SPI_CR1 register. If the NSS pin is required in output mode, the SSOE bit only should be set. This step is not required when the TI mode is selected. 6. Set the FRF bit in SPI_CR2 to select the TI protocol for serial communications. 7. The MSTR and SPE bits must be set (they remain set only if the NSS pin is connected to a high-level signal). In this configuration the MOSI pin is a data output and the MISO pin is a data input. Transmit sequence The transmit sequence begins when a byte is written in the Tx Buffer. The data byte is parallel-loaded into the shift register (from the internal bus) during the first bit transmission and then shifted out serially to the MOSI pin MSB first or LSB first depending on the LSBFIRST bit in the SPI_CR1 register. The TXE flag is set on the transfer of data from the Tx Buffer to the shift register and an interrupt is generated if the TXEIE bit in the SPI_CR2 register is set. Receive sequence For the receiver, when data transfer is complete: ● The data in the shift register is transferred to the RX Buffer and the RXNE flag is set ● An interrupt is generated if the RXNEIE bit is set in the SPI_CR2 register At the last sampling clock edge the RXNE bit is set, a copy of the data byte received in the shift register is moved to the Rx buffer. When the SPI_DR register is read, the SPI peripheral returns this buffered value. Clearing the RXNE bit is performed by reading the SPI_DR register. A continuous transmit stream can be maintained if the next data to be transmitted is put in the Tx buffer once the transmission is started. Note that TXE flag should be ‘1 before any attempt to write the Tx buffer is made. Note: When a master is communicating with SPI slaves which need to be de-selected between transmissions, the NSS pin must be configured as GPIO or another GPIO must be used and toggled by software. 799/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 9.5.5 D
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Interrupts and events RM0090 Table
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Basic timers (TIM6&TIM7) RM0090 17.
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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