RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Serial peripheral interface (SPI) SPI TI protocol in master mode In master mode, the SPI interface is compatible with the TI protocol. The FRF bit of the SPI_CR2 register can be used to configure the master SPI serial communications to be compliant with this protocol. The clock polarity and phase are forced to conform to the TI protocol requirements whatever the values set in the SPI_CR1 register. NSS management is also specific to the TI protocol which makes the configuration of NSS management through the SPI_CR1 and SPI_CR2 registers (SSM, SSI, SSOE) transparent for the user. Figure 275: TI mode - master mode, single transfer and Figure 276: TI mode - master mode, continuous transfer) show the SPI master communication waveforms when the TI mode is selected in master mode. Figure 275. TI mode - master mode, single transfer Figure 276. TI mode - master mode, continuous transfer NSS output SCK output MOSI output MISO intput NSS output SCK output MOSI input MISO output trigger edge sampling trigger edge edge sampling edge trigger edge sampling edge DONTCARE MSBIN LSBIN DONTCARE 1 or 0 MSBOUT LSBOUT trigger sampling trigger sampling trigger sampling DONTCARE MSBOUT LSBOUT 1 or 0 MSBIN LSBIN MSBOUT LSBOUT MSBIN LSBIN FRAME 1 FRAME 2 ai18436 DONTCARE ai18437 Doc ID 018909 Rev 3 800/1416
Serial peripheral interface (SPI) <strong>RM0090</strong> 27.3.4 Configuring the SPI for half-duplex communication The SPI is capable of operating in half-duplex mode in 2 configurations. ● 1 clock and 1 bidirectional data wire ● 1 clock and 1 data wire (receive-only or transmit-only) 1 clock and 1 bidirectional data wire (BIDIMODE=1) This mode is enabled by setting the BIDIMODE bit in the SPI_CR1 register. In this mode SCK is used for the clock and MOSI in master or MISO in slave mode is used for data communication. The transfer direction (Input/Output) is selected by the BIDIOE bit in the SPI_CR1 register. When this bit is 1, the data line is output otherwise it is input. 1 clock and 1 unidirectional data wire (BIDIMODE=0) In this mode, the application can use the SPI either in transmit-only mode or in receive-only mode. ● Transmit-only mode is similar to full-duplex mode (BIDIMODE=0, RXONLY=0): the data are transmitted on the transmit pin (MOSI in master mode or MISO in slave mode) and the receive pin (MISO in master mode or MOSI in slave mode) can be used as a general-purpose IO. In this case, the application just needs to ignore the Rx buffer (if the data register is read, it does not contain the received value). ● In receive-only mode, the application can disable the SPI output function by setting the RXONLY bit in the SPI_CR2 register. In this case, it frees the transmit IO pin (MOSI in master mode or MISO in slave mode), so it can be used for other purposes. To start the communication in receive-only mode, configure and enable the SPI: ● In master mode, the communication starts immediately and stops when the SPE bit is cleared and the current reception stops. There is no need to read the BSY flag in this mode. It is always set when an SPI communication is ongoing. ● In slave mode, the SPI continues to receive as long as the NSS is pulled down (or the SSI bit is cleared in NSS software mode) and the SCK is running. 27.3.5 Data transmission and reception procedures Rx and Tx buffers In reception, data are received and then stored into an internal Rx buffer while In transmission, data are first stored into an internal Tx buffer before being transmitted. A read access of the SPI_DR register returns the Rx buffered value whereas a write access to the SPI_DR stores the written data into the Tx buffer. 801/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 12.4.2 Independent
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 15 14 1
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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