RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Serial peripheral interface (SPI) 27.4 I 2 S functional description 27.4.1 I 2 S general description The block diagram of the I 2 S is shown in Figure 286. Figure 286. I 2 S block diagram MOSI/ SD MISO/ I2S2ext_SD/ I2S3ext_SD (1) NSS/WS CK MCK I2SMOD I2S_CK Master control logic SPI baud rate generator Tx buffer Shift register 1. I2S2ext_SD and I2S3ext_SD are the extended SD pins that control the I 2 S full duplex mode. The SPI could function as an audio I 2 S interface when the I 2 S capability is enabled (by setting the I2SMOD bit in the SPI_I2SCFGR register). This interface uses almost the same pins, flags and interrupts as the SPI. 16-bit Rx buffer 16-bit Bidi mode Address and data bus BSY OVR MODF CRC ERR Bidi OE LSB first I2SCFG I2SSTD CK DATLEN CH [1:0] [1:0] POL [1:0] LEN CRC EN CH TxE RxNE SIDE CRC Rx DFF Next only SSM SSI LSB First SPE BR2 BR1 BR0 MSTR CPOL CPHA I 2 S clock generator MCKOEODD I2SDIV[7:0] I2S MOD I2SE Communication control Doc ID 018909 Rev 3 816/1416 UDR I2SxCLK FRE MS19909V1
Serial peripheral interface (SPI) <strong>RM0090</strong> The I 2 S shares three common pins with the SPI: ● SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two timemultiplexed data channels (in half-duplex mode only). ● WS: Word Select (mapped on the NSS pin) is the data control signal output in master mode and input in slave mode. ● CK: Serial Clock (mapped on the SCK pin) is the serial clock output in master mode and serial clock input in slave mode. ● I2S2ext_SD and I2S3ext_SD: additional pins (mapped on the MISO pin) to control the I 2 S full duplex mode. An additional pin could be used when a master clock output is needed for some external audio devices: ● MCK: Master Clock (mapped separately) is used, when the I 2 S is configured in master mode (and when the MCKOE bit in the SPI_I2SPR register is set), to output this additional clock generated at a preconfigured frequency rate equal to 256 × FS , where FS is the audio sampling frequency. The I 2 S uses its own clock generator to produce the communication clock when it is set in master mode. This clock generator is also the source of the master clock output. Two additional registers are available in I 2 S mode. One is linked to the clock generator configuration SPI_I2SPR and the other one is a generic I 2 S configuration register SPI_I2SCFGR (audio standard, slave/master mode, data format, packet frame, clock polarity, etc.). The SPI_CR1 register and all CRC registers are not used in the I 2 S mode. Likewise, the SSOE bit in the SPI_CR2 register and the MODF and CRCERR bits in the SPI_SR are not used. The I 2 S uses the same SPI register for data transfer (SPI_DR) in 16-bit wide mode. 27.4.2 I2S full duplex To support I2S full duplex mode, two extra I 2 S instances called extended I2Ss (I2S2_ext, I2S3_ext) are available in addition to I2S2 and I2S3 (see Figure 287). The first I2S fullduplex interface is consequently based on I2S2 and I2S2_ext, and the second one on I2S3 and I2S3_ext. Note: I2S2_ext an I2S3_ext are used only in full-duplex mode. Figure 287. I2S full duplex block diagram I2Sx_SCK I2S_ WS 1. Where x can be 2 or 3. SPI/I2Sx I2Sx_ext 817/1416 Doc ID 018909 Rev 3 SPIx_MOSI/I2Sx_SD(in/out) I2Sx_extSD(in/out) MS19910V1
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 Table
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Real-time clock (RTC) RM0090 23.2 R
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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