RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Reset and clock control for (RCC) 6.3.9 RCC APB1 peripheral reset register for STM32F42x and STM32F43x (RCC_APB1RSTR) Address offset: 0x20 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UART8R UART7R DACRST ST ST PWR RST Reser- CAN2 RST CAN1 RST Reser- I2C3 RST I2C2 RST I2C1 RST UART5 RST UART4 RST UART3 RST UART2 RST Reservedvedved rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPI3 RST SPI2 RST Reserved WWDG RST Reserved TIM14 RST rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 UART8RST: UART8 reset Set and cleared by software. 0: does not reset UART8 1: resets UART8 Bits 30 UART7RST: UART7 reset Set and cleared by software. 0: does not reset UART7 1: resets UART7 Bit 29 DACRST: DAC reset Set and cleared by software. 0: does not reset the DAC interface 1: resets the DAC interface Bit 28 PWRRST: Power interface reset Set and cleared by software. 0: does not reset the power interface 1: resets the power interface Bit 27 Reserved, must be kept at reset value. Bit 26 CAN2RST: CAN2 reset Set and cleared by software. 0: does not reset CAN2 1: resets CAN2 Bit 25 CAN1RST: CAN1 reset Set and cleared by software. 0: does not reset CAN1 1: resets CAN1 Bit 24 Reserved, must be kept at reset value. Bit 23 I2C3RST: I2C3 reset Set and cleared by software. 0: does not reset I2C3 1: resets I2C3 TIM13 RST TIM12 RST TIM7 RST TIM6 RST TIM5 RST TIM4 RST TIM3 RST TIM2 RST Doc ID 018909 Rev 3 138/1416
Reset and clock control for (RCC) <strong>RM0090</strong> Bit 22 I2C2RST: I2C2 reset Set and cleared by software. 0: does not reset I2C2 1: resets I2C2 Bit 21 I2C1RST: I2C1 reset Set and cleared by software. 0: does not reset I2C1 1: resets I2C1 Bit 20 UART5RST: UART5 reset Set and cleared by software. 0: does not reset UART5 1: resets UART5 Bit 19 UART4RST: USART4 reset Set and cleared by software. 0: does not reset UART4 1: resets UART4 Bit 18 USART3RST: USART3 reset Set and cleared by software. 0: does not reset USART3 1: resets USART3 Bit 17 USART2RST: USART2 reset Set and cleared by software. 0: does not reset USART2 1: resets USART2 Bit 16 Reserved, must be kept at reset value. Bit 15 SPI3RST: SPI3 reset Set and cleared by software. 0: does not reset SPI3 1: resets SPI3 Bit 14 SPI2RST: SPI2 reset Set and cleared by software. 0: does not reset SPI2 1: resets SPI2 Bits 13:12 Reserved, must be kept at reset value. Bit 11 WWDGRST: Window watchdog reset Set and cleared by software. 0: does not reset the window watchdog 1: resets the window watchdog Bits 10:9 Reserved, must be kept at reset value. Bit 8 TIM14RST: TIM14 reset Set and cleared by software. 0: does not reset TIM14 1: resets TIM14 139/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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General-purpose I/Os (GPIO) RM0090
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System configuration controller (SY
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Analog-to-digital converter (ADC) R
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 The as
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Real-time clock (RTC) RM0090 23.3.5
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Real-time clock (RTC) RM0090 Bit 3
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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