RM0090: Reference manual - STMicroelectronics

RM0090 Ethernet (ETH): media access control (MAC) with DMA controller
PTP pulse-per-second output signal
This PTP pulse output is used to check the synchronization between all nodes in the
network. To be able to test the difference between the local slave clock and the master
reference clock, both clocks were given a pulse-per-second (PPS) output signal that may be
connected to an oscilloscope if necessary. The deviation between the two signals can
therefore be measured. The pulse width of the PPS output is 125 ms.
The PPS output is enabled through bits 11 and 10 in the TIM2 option register (TIM2_OR).
The default frequency of the PPS output is 1 Hz. PPSFREQ[3:0] (in ETH_PTPPPSCR) can
be used to set the frequency of the PPS output to 2 PPSFREQ Hz.
When set to 1 Hz, the PPS pulse width is 125 ms with binary rollover (TSSSR=0, bit 9 in
ETH_PTPTSCR) and 100 ms with digital rollover (TSSSR=1). When set to 2 Hz and higher,
the duty cycle of the PPS output is 50% with binary rollover.
With digital rollover (TSSSR=1), it is recommended not to use the PPS output with a
frequency other than 1 Hz as it would have irregular waveforms (though its average
frequency would always be correct during any one-second window).
Figure 345. PPS output
Ethernet MAC
PPS output
29.6 Ethernet functional description: DMA controller operation
ai15672
The DMA has independent transmit and receive engines, and a CSR space. The transmit
engine transfers data from system memory into the Tx FIFO while the receive engine
transfers data from the Rx FIFO into system memory. The controller utilizes descriptors to
efficiently move data from source to destination with minimum CPU intervention. The DMA
is designed for packet-oriented data transfers such as frames in Ethernet. The controller can
be programmed to interrupt the CPU in cases such as frame transmit and receive transfer
completion, and other normal/error conditions. The DMA and the STM32F4xx communicate
through two data structures:
● Control and status registers (CSR)
● Descriptor lists and data buffers.
Control and status registers are described in detail in Section 29.8 on page 968. Descriptors
are described in detail in Section on page 948.
The DMA transfers the received data frames to the receive buffer in the STM32F4xx
memory, and transmits data frames from the transmit buffer in the STM32F4xx memory.
Descriptors that reside in the STM32F4xx memory act as pointers to these buffers. There
are two descriptor lists: one for reception, and one for transmission. The base address of
each list is written into DMA Registers 3 and 4, respectively. A descriptor list is forwardlinked
(either implicitly or explicitly). The last descriptor may point back to the first entry to
create a ring structure. Explicit chaining of descriptors is accomplished by configuring the
second address chained in both the receive and transmit descriptors (RDES1[14] and
TDES0[20]). The descriptor lists reside in the Host’s physical memory space. Each
descriptor can point to a maximum of two buffers. This enables the use of two physically
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