RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Secure digital input/output interface (SDIO) 31 Table 157. SDIO register map (continued) Offset Register 0x38 SDIO_ICR 0x3C SDIO_MASK 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved CEATAENDC SDIOITC CEATAENDIE SDIOITIE RXDAVLIE Refer to Table 2 on page 53 for the register boundary addresses. TXDAVLIE RXFIFOEIE TXFIFOEIE Reserved RXFIFOFIE TXFIFOFIE RXFIFOHFIE TXFIFOHEIE RXACTIE TXACTIE CMDACTIE DBCKENDIE 0x48 SDIO_FIFOCNT Reserved FIFOCOUNT 0x80 SDIO_FIFO FIF0Data DBCKENDC STBITERRC STBITERRIE DATAENDIE DATAENDC CMDSENTC CMDSENTIE CMDRENDIE CMDRENDC RXOVERRC RXOVERRIE TXUNDERRIE TXUNDERRC DTIMEOUTC DTIMEOUTIE CTIMEOUTIE CTIMEOUTC DCRCFAILC Doc ID 018909 Rev 3 898/1416 CCRCFAILC DCRCFAILIE CCRCFAILIE
Ethernet (ETH): media access control (MAC) with DMA controller <strong>RM0090</strong> 29 Ethernet (ETH): media access control (MAC) with DMA controller This section applies to the whole STM32F4xx family, unless otherwise specified. 29.1 Ethernet introduction Portions Copyright (c) 2004, 2005 Synopsys, Inc. All rights reserved. Used with permission. The Ethernet peripheral enables the STM32F4xx to transmit and receive data over Ethernet in compliance with the IEEE 802.3-2002 standard. The Ethernet provides a configurable, flexible peripheral to meet the needs of various applications and customers. It supports two industry standard interfaces to the external physical layer (PHY): the default media independent interface (MII) defined in the IEEE 802.3 specifications and the reduced media independent interface (RMII). It can be used in number of applications such as switches, network interface cards, etc. The Ethernet is compliant with the following standards: ● IEEE 802.3-2002 for Ethernet MAC ● IEEE 1588-2008 standard for precision networked clock synchronization ● AMBA 2.0 for AHB Master/Slave ports ● RMII specification from RMII consortium 29.2 Ethernet main features The Ethernet (ETH) peripheral includes the following features, listed by category: 899/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 12.4.2 Independent
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 23.3.5
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 31 30 29
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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