RM0090: Reference manual - STMicroelectronics

Ethernet (ETH): media access control (MAC) with DMA controller RM0090
29.4 Ethernet functional description: SMI, MII and RMII
The Ethernet peripheral consists of a MAC 802.3 (media access control) with a dedicated
DMA controller. It supports both default media-independent interface (MII) and reduced
media-independent interface (RMII) through one selection bit (refer to SYSCFG_PMC
register).
The DMA controller interfaces with the Core and memories through the AHB Master and
Slave interfaces. The AHB Master Interface controls data transfers while the AHB Slave
interface accesses Control and Status Registers (CSR) space.
The Transmit FIFO (Tx FIFO) buffers data read from system memory by the DMA before
transmission by the MAC Core. Similarly, the Receive FIFO (Rx FIFO) stores the Ethernet
frames received from the line until they are transferred to system memory by the DMA.
The Ethernet peripheral also includes an SMI to communicate with external PHY. A set of
configuration registers permit the user to select the desired mode and features for the MAC
and the DMA controller.
Note: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.
Figure 320. ETH block diagram
AHB Slave interface
Bus matrix
DMA
control &
status
registers
Ethernet
DMA
Operation
mode
register
2 Kbyte
RX FIFO
2 Kbyte
TX FIFO
Media access
control
MAC 802.3
Checksum
offload
MAC
control
registers
1. For AHB connections please refer to Figure 1: System architecture for STM32F40x and STM32F41x
devices and Figure 2: System architecture for STM32F42x and STM32F43x devices.
29.4.1 Station management interface: SMI
PTP
IEEE1588
PMT MMC
The station management interface (SMI) allows the application to access any PHY registers
through a 2-wire clock and data lines. The interface supports accessing up to 32 PHYs.
The application can select one of the 32 PHYs and one of the 32 registers within any PHY
and send control data or receive status information. Only one register in one PHY can be
addressed at any given time.
Both the MDC clock line and the MDIO data line are implemented as alternate function I/O
in the microcontroller:
● MDC: a periodic clock that provides the timing reference for the data transfer at the
maximum frequency of 2.5 MHz. The minimum high and low times for MDC must be
903/1416 Doc ID 018909 Rev 3
RMII
Interface
MII
MDC
MDIO
Select
External PHY
ai15620c