RM0090: Reference manual - STMicroelectronics

Ethernet (ETH): media access control (MAC) with DMA controller RM0090
receive buffer unavailable (ETH_DMASR register[7]) occurs. The driver clears the Receive
interrupt. Even then, a new interrupt is generated, due to the active or pending Receive
buffer unavailable interrupt.
Figure 354. Interrupt scheme
TBUS
TBUIE
AND
TPSS
AND
TPSSIE
TUS
TUIE
AND
RWTS
AND
RWTIE
29.7 Ethernet interrupts
AND
AND
The Ethernet controller has two interrupt vectors: one dedicated to normal Ethernet
operations and the other, used only for the Ethernet wakeup event (with wakeup frame or
Magic Packet detection) when it is mapped on EXTI lIne19.
The first Ethernet vector is reserved for interrupts generated by the MAC and the DMA as
listed in the MAC interrupts and DMA interrupts sections.
The second vector is reserved for interrupts generated by the PMT on wakeup events. The
mapping of a wakeup event on EXTI line19 causes the STM32F4xx to exit the low power
mode, and generates an interrupt.
When an Ethernet wakeup event mapped on EXTI Line19 occurs and the MAC PMT
interrupt is enabled and the EXTI Line19 interrupt, with detection on rising edge, is also
enabled, both interrupts are generated.
A watchdog timer (see ETH_DMARSWTR register) is given for flexible control of the RS bit
(ETH_DMASR register). When this watchdog timer is programmed with a non-zero value, it
gets activated as soon as the RxDMA completes a transfer of a received frame to system
memory without asserting the Receive Status because it is not enabled in the corresponding
Receive descriptor (RDES1[31]). When this timer runs out as per the programmed value,
the RS bit is set and the interrupt is asserted if the corresponding RIE is enabled in the
967/1416 Doc ID 018909 Rev 3
RS
TS
TIE
RIE
FBES
FBEIE
ROS
ROIE
AND
AND
RBU
AND
RBUIE
ETS
ETIE
AND
ERS
ERIE
TJTS
TJTIE
AND
AND
RPSS
AND
RPSSIE
OR
OR
NIS
NISE
AIS
AISE
AND
AND
MMCI
PMTI
TSTI
OR
Interrupt
AI15646