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RM0090: Reference manual - STMicroelectronics

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USB on-the-go full-speed (OTG_FS) <strong>RM0090</strong><br />

STUPCNT: SETUP packet count<br />

Applies to control OUT Endpoints only.<br />

This field specifies the number of back-to-back SETUP data packets the endpoint can<br />

receive.<br />

01: 1 packet<br />

10: 2 packets<br />

11: 3 packets<br />

Bit 28:19 PKTCNT: Packet count<br />

Indicates the total number of USB packets that constitute the Transfer Size amount of data<br />

for this endpoint.<br />

This field is decremented every time a packet (maximum size or short packet) is written to<br />

the RxFIFO.<br />

Bits 18:0 XFRSIZ: Transfer size<br />

This field contains the transfer size in bytes for the current endpoint. The core only interrupts<br />

the application after it has exhausted the transfer size amount of data. The transfer size can<br />

be set to the maximum packet size of the endpoint, to be interrupted at the end of each<br />

packet.<br />

The core decrements this field every time a packet is read from the RxFIFO and written to<br />

the external memory.<br />

30.16.5 OTG_FS power and clock gating control register<br />

(OTG_FS_PCGCCTL)<br />

Address offset: 0xE00<br />

Reset value: 0x0000 0000<br />

This register is available in host and device modes.<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

Reserved<br />

Bit 31:5 Reserved, must be kept at reset value.<br />

1101/1416 Doc ID 018909 Rev 3<br />

PHYSUSP<br />

Reserved<br />

GATEHCLK<br />

STPPCLK<br />

rw rw rw<br />

Bit 4 PHYSUSP: PHY Suspended<br />

Indicates that the PHY has been suspended. This bit is updated once the PHY is suspended<br />

after the application has set the STPPCLK bit (bit 0).<br />

Bits 3:2 Reserved, must be kept at reset value.<br />

Bit 1 GATEHCLK: Gate HCLK<br />

The application sets this bit to gate HCLK to modules other than the AHB Slave and Master<br />

and wakeup logic when the USB is suspended or the session is not valid. The application<br />

clears this bit when the USB is resumed or a new session starts.<br />

Bit 0 STPPCLK: Stop PHY clock<br />

The application sets this bit to stop the PHY clock when the USB is suspended, the session<br />

is not valid, or the device is disconnected. The application clears this bit when the USB is<br />

resumed or a new session starts.

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