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RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Analog-to-digital converter (ADC)<br />

If the CONT bit is set on ADC1, ADC2 and ADC3, the selected regular channels of all ADCs<br />

are continuously converted.<br />

In this mode a DMA request is generated each time 2 data items are available, (if the<br />

DMA[1:0] bits in the ADC_CCR register are equal to 0b10). The request first transfers the<br />

first converted data stored in the lower half-word of the ADC_CDR 32-bit register to SRAM,<br />

then it transfers the second converted data stored in ADC_CDR’s upper half-word to SRAM.<br />

The sequence is the following:<br />

● 1st request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0]<br />

● 2nd request: ADC_CDR[31:0] = ADC1_DR[15:0] | ADC3_DR[15:0]<br />

● 3rd request: ADC_CDR[31:0] = ADC3_DR[15:0] | ADC2_DR[15:0]<br />

● 4th request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0], ...<br />

Figure 47. Interleaved mode on 1 channel in continuous conversion mode: triple<br />

ADC mode<br />

ADC1<br />

ADC2<br />

ADC3<br />

Trigger<br />

11.9.4 Alternate trigger mode<br />

This mode can be started only on an injected group. The source of external trigger comes<br />

from the injected group multiplexer of ADC1.<br />

Note: Regular conversions can be enabled on one or all ADCs. In this case the regular<br />

conversions are independent of each other. A regular conversion is interrupted when the<br />

ADC has to perform an injected conversion. It is resumed when the injected conversion is<br />

finished.<br />

The time interval between 2 trigger events must be greater than or equal to 1 ADC clock<br />

period. The minimum time interval between 2 trigger events that start conversions on the<br />

same ADC is the same as in the single ADC mode.<br />

Dual ADC mode<br />

CH0<br />

6 ADCCLK<br />

cycles<br />

CH0<br />

CH0<br />

End of conversion on ADC1<br />

DMA request every 2 conversions<br />

CH0<br />

CH0<br />

...<br />

CH0<br />

...<br />

...<br />

End of conversion on ADC3<br />

End of conversion on ADC2<br />

● When the 1st trigger occurs, all injected ADC1 channels in the group are converted<br />

● When the 2nd trigger occurs, all injected ADC2 channels in the group are converted<br />

● and so on<br />

A JEOC interrupt, if enabled, is generated after all injected ADC1 channels in the group<br />

have been converted.<br />

CH0<br />

CH0<br />

CH0<br />

Sampling<br />

Conversion<br />

ai16058<br />

Doc ID 018909 Rev 3 282/1416

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