RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Digital-to-analog converter (DAC) 12.5.12 DAC channel1 data output register (DAC_DOR1) Address offset: 0x2C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DACC1DOR[11:0] Reserved r r r r r r r r r r r r Bits 31:12 Reserved, must be kept at reset value. Bit 11:0 DACC1DOR[11:0]: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. 12.5.13 DAC channel2 data output register (DAC_DOR2) Address offset: 0x30 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DACC2DOR[11:0] Reserved r r r r r r r r r r r r Bits 31:12 Reserved, must be kept at reset value. Bit 11:0 DACC2DOR[11:0]: DAC channel2 data output These bits are read-only, they contain data output for DAC channel2. 12.5.14 DAC status register (DAC_SR) Address offset: 0x34 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DMAUDR2 Reserved rc_w1 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAUDR1 Reserved rc_w1 Reserved Doc ID 018909 Rev 3 324/1416
Digital-to-analog converter (DAC) <strong>RM0090</strong> Bits 31:30 Reserved, must be kept at reset value. Bit 29 DMAUDR2: DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 0: No DMA underrun error condition occurred for DAC channel2 1: DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is driving DAC channel2 conversion at a frequency higher than the DMA service capability rate) Bits 28:14 Reserved, must be kept at reset value. Bit 13 DMAUDR1: DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 0: No DMA underrun error condition occurred for DAC channel1 1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) Bits 12:0 Reserved, must be kept at reset value. 12.5.15 DAC register map Table 57 summarizes the DAC registers. Table 57. DAC register map Address offset Register name 31 0x00 DAC_CR 0x04 DAC_SWT RIGR Reserved 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAUDRIE2 DMAEN2 MAMP2[3:0] WAVE 2[2:0] TSEL2[2:0] Refer to Table 2 on page 53 for the register boundary addresses. 325/1416 Doc ID 018909 Rev 3 TEN2 BOFF2 EN2 Reserved Reserved DMAUDRIE1 DMAEN1 MAMP1[3:0] WAVE 1[2:0] TSEL1[2:0] 0x08 DAC_DHR1 2R1 Reserved DACC1DHR[11:0] 0x0C DAC_DHR1 2L1 Reserved DACC1DHR[11:0] Reserved 0x10 DAC_DHR8 R1 Reserved DACC1DHR[7:0] 0x14 DAC_DHR1 2R2 Reserved DACC2DHR[11:0] 0x18 DAC_DHR1 2L2 Reserved DACC2DHR[11:0] Reserved 0x1C DAC_DHR8 R2 Reserved DACC2DHR[7:0] 0x20 DAC_DHR1 2RD Reserved DACC2DHR[11:0] Reserved DACC1DHR[11:0] 0x24 DAC_DHR1 2LD DACC2DHR[11:0] Reserved DACC1DHR[11:0] Reserved 0x28 DAC_DHR8 RD Reserved DACC2DHR[7:0] DACC1DHR[7:0] 0x2C DAC_DOR1 Reserved DACC1DOR[11:0] 0x30 DAC_DOR2 Reserved DACC2DOR[11:0] 0x34 DAC_SR Reserved DMAUDR2 Reserved DMAUDR1 Reserved TEN1 BOFF1 EN1 SWTRIG2 SWTRIG1
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Analog-to-digital converter (ADC) R
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Basic timers (TIM6&TIM7) RM0090 17.
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 Table
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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