RM0090: Reference manual - STMicroelectronics

Memory and bus architecture RM0090
Figure 2. System architecture for STM32F42x and STM32F43x devices
64-Kbyte
CCM data RAM
I-bus
2.1.1 S0: I-bus
ARM
Cortex-M4
D-bus
This bus connects the Instruction bus of the Cortex-M4F core to the BusMatrix. This bus
is used by the core to fetch instructions. The target of this bus is a memory containing code
(internal Flash memory/SRAM or external memories through the FSMC).
2.1.2 S1: D-bus
This bus connects the databus of the Cortex-M4F and the 64-Kbyte CCM data RAM to the
BusMatrix. This bus is used by the core for literal load and debug access. The target of this
bus is a memory containing code or data (internal Flash memory or external memories
through the FSMC).
2.1.3 S2: S-bus
S-bus
GP
DMA1
Bus matrix-S
This bus connects the system bus of the Cortex-M4F core to a BusMatrix. This bus is
used to access data located in a peripheral or in SRAM. Instructions may also be fetch on
this bus (less efficient than ICode). The targets of this bus are the 112, 64, and 16 Kbytes
internal SRAMs, the AHB1 peripherals including the APB peripherals, the AHB2 peripherals
and the external memories through the FSMC.
2.1.4 S3, S4: DMA memory bus
GP
DMA2
MAC
Ethernet
S0 S1 S2 S3 S4 S5 S6 S7
This bus connects the DMA memory bus master interface to the BusMatrix. It is used by the
DMA to perform transfer to/from memories. The targets of this bus are data memories:
internal SRAMs (112, 64, and 16 Kbytes) and external memories through the FSMC.
51/1416 Doc ID 018909 Rev 3
DMA_PI
DMA_MEM1
DMA_MEM2
DMA_P2
ETHERNET_M
USB OTG
HS
USB_HS_M
M0
M1
M2
M3
M4
M5
M6
M7
ICODE
DCODE
ACCEL
Flash
memory
SRAM
112 Kbyte
SRAM
16 Kbyte
AHB2
peripherals
AHB2
peripherals
FSMC
Static MemCtl
SRAM
64 Kbyte
APB1
APB2
MS30410V2