RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Analog-to-digital converter (ADC) Bit 22 JSWSTART: Start conversion of injected channels This bit is set by software and cleared by hardware as soon as the conversion starts. 0: Reset state 1: Starts conversion of injected channels Note: This bit can be set only when ADON = 1 otherwise no conversion is launched. Bits 21:20 JEXTEN: External trigger enable for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. 00: Trigger detection disabled 01: Trigger detection on the rising edge 10: Trigger detection on the falling edge 11: Trigger detection on both the rising and falling edges Bits 19:16 JEXTSEL[3:0]: External event select for injected group These bits select the external event used to trigger the start of conversion of an injected group. 0000: Timer 1 CC4 event 0001: Timer 1 TRGO event 0010: Timer 2 CC1 event 0011: Timer 2 TRGO event 0100: Timer 3 CC2 event 0101: Timer 3 CC4 event 0110: Timer 4 CC1 event 0111: Timer 4 CC2 event 1000: Timer 4 CC3 event 1001: Timer 4 TRGO event 1010: Timer 5 CC4 event 1011: Timer 5 TRGO event 1100: Timer 8 CC2 event 1101: Timer 8 CC3 event 1110: Timer 8 CC4 event 1111: EXTI line15 Bits 15:12 Reserved, must be kept at reset value. Bit 11 ALIGN: Data alignment This bit is set and cleared by software. Refer to Figure 38 and Figure 39. 0: Right alignment 1: Left alignment Bit 10 EOCS: End of conversion selection This bit is set and cleared by software. 0: The EOC bit is set at the end of each sequence of regular conversions. Overrun detection is enabled only if DMA=1. 1: The EOC bit is set at the end of each regular conversion. Overrun detection is enabled. Bit 9 DDS: DMA disable selection (for single ADC mode) This bit is set and cleared by software. 0: No new DMA request is issued after the last transfer (as configured in the DMA controller) 1: DMA requests are issued as long as data are converted and DMA=1 Bit 8 DMA: Direct memory access mode (for single ADC mode) This bit is set and cleared by software. Refer to the DMA controller chapter for more details. 0: DMA mode disabled 1: DMA mode enabled Doc ID 018909 Rev 3 292/1416
Analog-to-digital converter (ADC) <strong>RM0090</strong> Bits 7:2 Reserved, must be kept at reset value. Bit 1 CONT: Continuous conversion This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. 0: Single conversion mode 1: Continuous conversion mode Bit 0 ADON: A/D Converter ON / OFF This bit is set and cleared by software. Note: 0: Disable ADC conversion and go to power down mode 1: Enable ADC 293/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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Reset and clock control for (RCC) R
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System configuration controller (SY
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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Digital camera interface (DCMI) RM0
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Cryptographic processor (CRYP) RM00
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 The as
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Real-time clock (RTC) RM0090 23.3.5
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Real-time clock (RTC) RM0090 The fo
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Real-time clock (RTC) RM0090 Sectio
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Real-time clock (RTC) RM0090 Bit 3
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Table 22
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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