RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> USB on-the-go full-speed (OTG_FS) OTG_FS Host non-periodic transmit FIFO size register (OTG_FS_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_FS_DIEPTXF0) Address offset: 0x028 Reset value: 0x0000 0200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Host mode Device mode NPTXFD/TX0FD NPTXFSA/TX0FSA r/rw r/rw Bits 31:16 NPTXFD: Non-periodic TxFIFO depth This value is in terms of 32-bit words. Minimum value is 16 Maximum value is 256 Bits 15:0 NPTXFSA: Non-periodic transmit RAM start address This field contains the memory start address for non-periodic transmit FIFO RAM. Bits 31:16 TX0FD: Endpoint 0 TxFIFO depth This value is in terms of 32-bit words. Minimum value is 16 Maximum value is 256 Bits 15:0 TX0FSA: Endpoint 0 transmit RAM start address This field contains the memory start address for the endpoint 0 transmit FIFO RAM. OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_HNPTXSTS) Address offset: 0x02C Reset value: 0x0008 0200 Note: In Device mode, this register is not valid. This read-only register contains the free space information for the non-periodic TxFIFO and the non-periodic transmit request queue. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved NPTXQTOP NPTQXSAV NPTXFSAV r r r Doc ID 018909 Rev 3 1064/1416
USB on-the-go full-speed (OTG_FS) <strong>RM0090</strong> Bit 31 Reserved, must be kept at reset value. Bits 30:24 NPTXQTOP: Top of the non-periodic transmit request queue Entry in the non-periodic Tx request queue that is currently being processed by the MAC. Bits 30:27: Channel/endpoint number Bits 26:25: – 00: IN/OUT token – 01: Zero-length transmit packet (device IN/host OUT) – 11: Channel halt command Bit 24: Terminate (last entry for selected channel/endpoint) Bits 23:16 NPTQXSAV: Non-periodic transmit request queue space available Indicates the amount of free space available in the non-periodic transmit request queue. This queue holds both IN and OUT requests in host mode. Device mode has only IN requests. 00: Non-periodic transmit request queue is full 01: 1 location available 10: 2 locations available bxn: n locations available (0 ≤ n ≤ 8) Others: Reserved Bits 15:0 NPTXFSAV: Non-periodic TxFIFO space available Indicates the amount of free space available in the non-periodic TxFIFO. Values are in terms of 32-bit words. 00: Non-periodic TxFIFO is full 01: 1 word available 10: 2 words available 0xn: n words available (where 0 ≤ n ≤ 256) Others: Reserved OTG_FS general core configuration register (OTG_FS_GCCFG) Address offset: 0x038 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 1065/1416 Doc ID 018909 Rev 3 NOVBUSSENS SOFOUTEN VBUSBSEN VBUSASEN Reserved .PWRDWN rw rw rw rw rw Reserved
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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Reset and clock control for (RCC) R
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System configuration controller (SY
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Analog-to-digital converter (ADC) R
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Cryptographic processor (CRYP) RM00
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 The as
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Real-time clock (RTC) RM0090 23.3.5
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Real-time clock (RTC) RM0090 The fo
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Real-time clock (RTC) RM0090 Sectio
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Real-time clock (RTC) RM0090 23.6 R
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Real-time clock (RTC) RM0090 Bit 3
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Controller area network (bxCAN) RM0
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Table 22
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 33.11 Ca
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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