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RM0090: Reference manual - STMicroelectronics

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Ethernet (ETH): media access control (MAC) with DMA controller <strong>RM0090</strong><br />

Ethernet MAC address 0 low register (ETH_MACA0LR)<br />

Address offset: 0x0044<br />

Reset value: 0xFFFF FFFF<br />

The MAC address 0 low register holds the lower 32 bits of the 6-byte first MAC address of<br />

the station.<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

MACA0L<br />

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw<br />

Bits 31:0 MACA0L: MAC address0 low [31:0]<br />

This field contains the lower 32 bits of the 6-byte MAC address0. This is used by the MAC<br />

for filtering for received frames and for inserting the MAC address in the transmit flow control<br />

(Pause) frames.<br />

Ethernet MAC address 1 high register (ETH_MACA1HR)<br />

Address offset: 0x0048<br />

Reset value: 0x0000 FFFF<br />

The MAC address 1 high register holds the upper 16 bits of the 6-byte second MAC address<br />

of the station.<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

AE SA MBC<br />

MACA1H<br />

Reserved<br />

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw<br />

Bit 31 AE: Address enable<br />

When this bit is set, the address filters use the MAC address1 for perfect filtering. When this<br />

bit is cleared, the address filters ignore the address for filtering.<br />

Bit 30 SA: Source address<br />

When this bit is set, the MAC address1[47:0] is used for comparison with the SA fields of the<br />

received frame.<br />

When this bit is cleared, the MAC address1[47:0] is used for comparison with the DA fields of<br />

the received frame.<br />

Bits 29:24 MBC: Mask byte control<br />

These bits are mask control bits for comparison of each of the MAC address1 bytes. When<br />

they are set high, the MAC core does not compare the corresponding byte of received<br />

DA/SA with the contents of the MAC address1 registers. Each bit controls the masking of the<br />

bytes as follows:<br />

– Bit 29: ETH_MACA1HR [15:8]<br />

– Bit 28: ETH_MACA1HR [7:0]<br />

– Bit 27: ETH_MACA1LR [31:24]<br />

…<br />

– Bit 24: ETH_MACA1LR [7:0]<br />

Bits 23:16 Reserved, must be kept at reset value.<br />

983/1416 Doc ID 018909 Rev 3

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