RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Interrupts and events Table 43. Vector table for STM32F40x and STM32F41x Position Priority Type of priority Acronym Description Address - - - Reserved 0x0000 0000 -3 fixed Reset Reset 0x0000 0004 -2 fixed NMI Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector. 0x0000 0008 -1 fixed HardFault All class of fault 0x0000 000C 0 settable MemManage Memory management 0x0000 0010 1 settable BusFault 2 settable UsageFault - - - Reserved 3 settable SVCall Pre-fetch fault, memory access fault Undefined instruction or illegal state System service call via SWI instruction 0x0000 0014 0x0000 0018 0x0000 001C - 0x0000 002B 0x0000 002C 4 settable Debug Monitor Debug Monitor 0x0000 0030 - - - Reserved 0x0000 0034 5 settable PendSV Pendable request for system service 0x0000 0038 6 settable SysTick System tick timer 0x0000 003C 0 7 settable WWDG Window Watchdog interrupt 0x0000 0040 1 8 settable PVD PVD through EXTI line detection interrupt 0x0000 0044 2 9 settable TAMP_STAMP 3 10 settable RTC_WKUP Tamper and TimeStamp interrupts through the EXTI line RTC Wakeup interrupt through the EXTI line 0x0000 0048 0x0000 004C 4 11 settable FLASH Flash global interrupt 0x0000 0050 5 12 settable RCC RCC global interrupt 0x0000 0054 6 13 settable EXTI0 EXTI Line0 interrupt 0x0000 0058 7 14 settable EXTI1 EXTI Line1 interrupt 0x0000 005C 8 15 settable EXTI2 EXTI Line2 interrupt 0x0000 0060 9 16 settable EXTI3 EXTI Line3 interrupt 0x0000 0064 10 17 settable EXTI4 EXTI Line4 interrupt 0x0000 0068 11 18 settable DMA1_Stream0 DMA1 Stream0 global interrupt 0x0000 006C 12 19 settable DMA1_Stream1 DMA1 Stream1 global interrupt 0x0000 0070 13 20 settable DMA1_Stream2 DMA1 Stream2 global interrupt 0x0000 0074 Doc ID 018909 Rev 3 248/1416
Interrupts and events <strong>RM0090</strong> Table 43. Vector table for STM32F40x and STM32F41x (continued) Position Priority Type of priority 14 21 settable DMA1_Stream3 DMA1 Stream3 global interrupt 0x0000 0078 15 22 settable DMA1_Stream4 DMA1 Stream4 global interrupt 0x0000 007C 16 23 settable DMA1_Stream5 DMA1 Stream5 global interrupt 0x0000 0080 17 24 settable DMA1_Stream6 DMA1 Stream6 global interrupt 0x0000 0084 18 25 settable ADC ADC1, ADC2 and ADC3 global interrupts 0x0000 0088 19 26 settable CAN1_TX CAN1 TX interrupts 0x0000 008C 20 27 settable CAN1_RX0 CAN1 RX0 interrupts 0x0000 0090 21 28 settable CAN1_RX1 CAN1 RX1 interrupt 0x0000 0094 22 29 settable CAN1_SCE CAN1 SCE interrupt 0x0000 0098 23 30 settable EXTI9_5 EXTI Line[9:5] interrupts 0x0000 009C 24 31 settable TIM1_BRK_TIM9 TIM1 Break interrupt and TIM9 global interrupt 0x0000 00A0 25 32 settable TIM1_UP_TIM10 26 33 settable TIM1_TRG_COM_T IM11 249/1416 Doc ID 018909 Rev 3 TIM1 Update interrupt and TIM10 global interrupt TIM1 Trigger and Commutation interrupts and TIM11 global interrupt 0x0000 00A4 0x0000 00A8 27 34 settable TIM1_CC TIM1 Capture Compare interrupt 0x0000 00AC 28 35 settable TIM2 TIM2 global interrupt 0x0000 00B0 29 36 settable TIM3 TIM3 global interrupt 0x0000 00B4 30 37 settable TIM4 TIM4 global interrupt 0x0000 00B8 31 38 settable I2C1_EV I 2 C1 event interrupt 0x0000 00BC 32 39 settable I2C1_ER I 2 C1 error interrupt 0x0000 00C0 33 40 settable I2C2_EV I 2 C2 event interrupt 0x0000 00C4 34 41 settable I2C2_ER I 2 C2 error interrupt 0x0000 00C8 35 42 settable SPI1 SPI1 global interrupt 0x0000 00CC 36 43 settable SPI2 SPI2 global interrupt 0x0000 00D0 37 44 settable USART1 USART1 global interrupt 0x0000 00D4 38 45 settable USART2 USART2 global interrupt 0x0000 00D8 39 46 settable USART3 USART3 global interrupt 0x0000 00DC 40 47 settable EXTI15_10 EXTI Line[15:10] interrupts 0x0000 00E0 41 48 settable RTC_Alarm 42 49 settable OTG_FS WKUP Acronym Description Address RTC Alarms (A and B) through EXTI line interrupt USB On-The-Go FS Wakeup through EXTI line interrupt 0x0000 00E4 0x0000 00E8
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Debug support (DBG) RM0090 33 Debug
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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