RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Random number generator (RNG) Bit 2 SECS: Seed error current status 0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered. 1: One of the following faulty sequences has been detected: – More than 64 consecutive bits at the same value (0 or 1) – More than 32 consecutive alternances of 0 and 1 (0101010101...01) Bit 1 CECS: Clock error current status 0: The PLL48CLK clock has been correctly detected. If the CEIS bit is set, this means that a clock error was detected and the situation has been recovered 1: The PLL48CLK was not correctly detected (f PLL48CLK< f HCLK/16). Bit 0 DRDY: Data ready 0: The RNG_DR register is not yet valid, no random data is available 1: The RNG_DR register contains valid random data Note: An interrupt is pending if IE = 1 in the RNG_CR register. Once the RNG_DR register has been read, this bit returns to 0 until a new valid value is computed. 21.4.3 RNG data register (RNG_DR) Address offset: 0x08 Reset value: 0x0000 0000 The RNG_DR register is a read-only register that delivers a 32-bit random value when read. After being read, this register delivers a new random value after a maximum time of 40 periods of the PLL48CLK clock. The software must check that the DRDY bit is set before reading the RNDATA value. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RNDATA r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RNDATA r r r r r r r r r r r r r r r r Bits 31:0 RNDATA: Random data 32-bit random data. Doc ID 018909 Rev 3 592/1416
Random number generator (RNG) <strong>RM0090</strong> 21.4.4 RNG register map Table 92 gives the RNG register map and reset values. Table 92. RNG register map and reset map Register name Offset reset value 0x00 0x04 0x08 RNG_CR 0x0000000 RNG_SR 0x0000000 RNG_DR 0x0000000 593/1416 Doc ID 018909 Rev 3 Register size 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved IE RNDATA[31:0] SEIS CEIS Reserved RNGEN SECS CECS Reserved DRDY
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Real-time clock (RTC) RM0090 Bit 4
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Real-time clock (RTC) RM0090 23.6.7
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Real-time clock (RTC) RM0090 Bit 0
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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