RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Ethernet (ETH): media access control (MAC) with DMA controller Ethernet DMA current host transmit descriptor register (ETH_DMACHTDR) Address offset: 0x1048 Reset value: 0x0000 0000 The Current host transmit descriptor register points to the start address of the current transmit descriptor read by the DMA. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HTDAP r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r Bits 31:0 HTDAP: Host transmit descriptor address pointer Cleared on reset. Pointer updated by DMA during operation. Ethernet DMA current host receive descriptor register (ETH_DMACHRDR) Address offset: 0x104C Reset value: 0x0000 0000 The Current host receive descriptor register points to the start address of the current receive descriptor read by the DMA. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HRDAP r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r Bits 31:0 HRDAP: Host receive descriptor address pointer Cleared on Reset. Pointer updated by DMA during operation. Ethernet DMA current host transmit buffer address register (ETH_DMACHTBAR) Address offset: 0x1050 Reset value: 0x0000 0000 The Current host transmit buffer address register points to the current transmit buffer address being read by the DMA. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HTBAP r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r Bits 31:0 HTBAP: Host transmit buffer address pointer Cleared on reset. Pointer updated by DMA during operation. Doc ID 018909 Rev 3 1012/1416
Ethernet (ETH): media access control (MAC) with DMA controller <strong>RM0090</strong> Ethernet DMA current host receive buffer address register (ETH_DMACHRBAR) Address offset: 0x1054 Reset value: 0x0000 0000 The current host receive buffer address register points to the current receive buffer address being read by the DMA. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 29.8.5 Ethernet register maps HRBAP r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r Bits 31:0 HRBAP: Host receive buffer address pointer Cleared on reset. Pointer updated by DMA during operation. Table 168 gives the ETH register map and reset values. Table 168. Ethernet register map and reset values Offset Register 31 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x28 ETH_MACCR 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CSTF eserved WD JD 1013/1416 Doc ID 018909 Rev 3 Reserved IFG CSD Reserved FES ROD LM HPF Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACFF RA R Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACHT HR HTH[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACHT LR HTL[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACMII AR Reserved PA MR M W M B Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACMII DR Reserved MD Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACFC R PT DM Reserved IPCO RD SAF Reserved APCS ZQPD PCF Reserved BL BFD PAM DC TE PLT RE Reserved DAIF HM HU PM Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACVL ANTR Reserved VLANTC VLANTI Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETH_MACRW UFFR Frame filter reg0\Frame filter reg1\Frame filter reg2\Frame filter reg3\Frame filter reg4\...\Frame filter reg7 Reset value 0 0x2C ETH_MACPM TCSR WFFRPR Reserved GU Reserved WFR MPR CR Reserved UPFD RFCE TFCE FCB/BPA WFE MPE PD Reset value 0 0 0 0 0 0 0
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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Reset and clock control for (RCC) R
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System configuration controller (SY
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Cryptographic processor (CRYP) RM00
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 The as
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Real-time clock (RTC) RM0090 23.3.5
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Real-time clock (RTC) RM0090 Bit 3
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 31 30 29
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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