RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Flexible static memory controller (FSMC) The FSMC registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next reset or power-up. However, it is possible to change the settings at any time. 32.2 Block diagram The FSMC consists of four main blocks: ● The AHB interface (including the FSMC configuration registers) ● The NOR Flash/PSRAM controller ● The NAND Flash/PC Card controller ● The external device interface The block diagram is shown in Figure 402. Figure 402. FSMC block diagram From clock controller HCLK FSMC interrupt to NVIC AHB bus Configuration Registers NOR memory controller NAND/PC Card memory controller FSMC_NE[4:1] FSMC_NL (or NADV) FSMC_NBL[1:0] FSMC_CLK FSMC_A[25:0] FSMC_D[15:0] FSMC_NOE FSMC_NWE FSMC_NWAIT FSMC_NCE[3:2] FSMC_INT[3:2] FSMC_INTR FSMC_NCE4_1 FSMC_NCE4_2 FSMC_NIORD FSMC_NIOWR FSMC_NREG FSMC_CD NOR/PSRAM signals Shared signals NAND signals PC Card signals ai15591 Doc ID 018909 Rev 3 1314/1416
Flexible static memory controller (FSMC) <strong>RM0090</strong> 32.3 AHB interface The AHB slave interface enables internal CPUs and other bus master peripherals to access the external static memories. AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16 or 8 bits wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses. The Chip Select toggles for each access. The FSMC generates an AHB error in the following conditions: ● When reading or writing to an FSMC bank which is not enabled ● When reading or writing to the NOR Flash bank while the FACCEN bit is reset in the FSMC_BCRx register. ● When reading or writing to the PC Card banks while the input pin FSMC_CD (Card Presence Detection) is low. The effect of this AHB error depends on the AHB master which has attempted the R/W access: ● If it is the Cortex-M4F CPU, a hard fault interrupt is generated ● If is a DMA, a DMA transfer error is generated and the corresponding DMA channel is automatically disabled. The AHB clock (HCLK) is the reference clock for the FSMC. 32.3.1 Supported memories and transactions General transaction rules The requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the accessed external device has a fixed data width. This may lead to inconsistent transfers. Therefore, some simple transaction rules must be followed: ● AHB transaction size and memory data size are equal There is no issue in this case. ● AHB transaction size is greater than the memory size In this case, the FSMC splits the AHB transaction into smaller consecutive memory accesses in order to meet the external data width. ● AHB transaction size is smaller than the memory size Asynchronous transfers may or not be consistent depending on the type of external device. – Asynchronous accesses to devices that have the byte select feature (SRAM, ROM, PSRAM). a) FSMC allows write transactions accessing the right data through its byte lanes NBL[1:0] b) Read transactions are allowed. All memory bytes are read and the useless ones are discarded. The NBL[1:0] are kept low during read transactions. – Asynchronous accesses to devices that do not have the byte select feature (NOR and NAND Flash 16-bit). This situation occurs when a byte access is requested to a 16-bit wide Flash 1315/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 12.4.2 Independent
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 The as
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Real-time clock (RTC) RM0090 23.3.5
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Real-time clock (RTC) RM0090 The fo
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Real-time clock (RTC) RM0090 Bit 3
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Flexible static memory controller (
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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