RM0090: Reference manual - STMicroelectronics

RM0090 Ethernet (ETH): media access control (MAC) with DMA controller
ETH_DMAIER register. This timer is disabled before it runs out, when a frame is transferred
to memory and the RS is set because it is enabled for that descriptor.
Note: Reading the PMT control and status register automatically clears the Wakeup Frame
Received and Magic Packet Received PMT interrupt flags. However, since the registers for
these flags are in the CLK_RX domain, there may be a significant delay before this update is
visible by the firmware. The delay is especially long when the RX clock is slow (in 10 Mbit
mode) and when the AHB bus is high-frequency.
Since interrupt requests from the PMT to the CPU are based on the same registers in the
CLK_RX domain, the CPU may spuriously call the interrupt routine a second time even after
reading PMT_CSR. Thus, it may be necessary that the firmware polls the Wakeup Frame
Received and Magic Packet Received bits and exits the interrupt service routine only when
they are found to be at ‘0’.
29.8 Ethernet register descriptions
The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32bits).
29.8.1 MAC register description
Ethernet MAC configuration register (ETH_MACCR)
Address offset: 0x0000
Reset value: 0x0000 8000
The MAC configuration register is the operation mode register of the MAC. It establishes
receive and transmit operating modes.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved CSTF
Reserved
WD
JD
Reserved
IFG
CSD
Reserved
FES
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:246 Reserved, must be kept at reset value.
Bits 25 CSTF: CRC stripping for Type frames
When set, the last 4 bytes (FCS) of all frames of Ether type (type field greater than
0x0600) will be stripped and dropped before forwarding the frame to the application.
Bits 24 Reserved, must be kept at reset value.
Bit 23 WD: Watchdog disable
When this bit is set, the MAC disables the watchdog timer on the receiver, and can receive
frames of up to 16 384 bytes.
When this bit is reset, the MAC allows no more than 2 048 bytes of the frame being received
and cuts off any bytes received after that.
Bit 22 JD: Jabber disable
When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer
frames of up to 16 384 bytes.
When this bit is reset, the MAC cuts off the transmitter if the application sends out more than
2 048 bytes of data during transmission.
ROD
LM
DM
IPCO
RD
Doc ID 018909 Rev 3 968/1416
Reserved
APCS
BL
DC
TE
RE
Reserved